Patents by Inventor Evgeny Levin

Evgeny Levin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DESIGN-BASED MONITORING
    Publication number: 20090007030
    Abstract: A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in a layer of the IC that is susceptible to a process fault. Upon fabricating the layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in the layer responsively to the PDP.
    Type: Application
    Filed: October 3, 2006
    Publication date: January 1, 2009
    Inventors: Youval Nehmadi, Josephine Phua, Jacob Joseph Orbon, JR., Ariel Ben-Porath, Evgeny Levin, Ofer Bokobza
  • Design-based monitoring
    Patent number: 7135344
    Abstract: A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault. Upon fabricating at least one layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in at least one layer responsively to the PDP.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: November 14, 2006
    Assignee: Applied Materials, Israel, Ltd.
    Inventors: Youval Nehmadi, Josephine Phua, Jacob Joseph Orbon, Jr., Ariel Ben-Porath, Evgeny Levin, Ofer Bokobza
  • Design-based monitoring
    Publication number: 20050010890
    Abstract: A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault. Upon fabricating at least one layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in at least one layer responsively to the PDP.
    Type: Application
    Filed: February 17, 2004
    Publication date: January 13, 2005
    Inventors: Youval Nehmadi, Josephine Phua, Jacob Orbon, Ariel Ben-Porath, Evgeny Levin, Ofer Bokobza