Abstract: An integrated electro-static discharge (ESD) device has a set of metal layers. Each metal layer in the set has one or more first-terminal metal features interleaved with one or more second-terminal metal features in a lateral direction, and at least one first-terminal metal feature in a metal layer of the set overlaps in a normal direction at least one second-terminal metal feature in an adjacent metal layer of the set. By overlapping metal features in the normal direction, capacitance can be added to the ESD device, which improves its operating characteristics, without increasing the layout size of the ESD device.

Abstract: There is disclosed herein an SOI IC comprising an integrated capacitor comprising a parallel arrangement of a metal-insulator-metal, MIM, capacitor, a second capacitor, a third capacitor, and a fourth capacitor: wherein the second capacitor comprises as plates the substrate and a one of a plurality of semiconductor layers having an n-type doping, and comprises the buried oxide layer as dielectric; the third capacitor comprises as plates the polysilicon layer and a further one of a plurality of semiconductor layers having an n-type doping, and comprises an insulating layer between the plurality of semiconductor layers and the metallisation stack as dielectric; and the fourth capacitor comprises as plates the polysilicon plug and at least one of the plurality of semiconductor layers and comprises the oxide-lining as dielectric, wherein the oxide lining and the polysilicon plug form part of a lateral isolation (DTI) structure.

Abstract: There is disclosed herein an SOI IC comprising an integrated capacitor comprising a parallel arrangement of a metal-insulator-metal, MIM, capacitor, a second capacitor, a third capacitor, and a fourth capacitor: wherein the second capacitor comprises as plates the substrate and a one of a plurality of semiconductor layers having an n-type doping, and comprises the buried oxide layer as dielectric; the third capacitor comprises as plates the polysilicon layer and a further one of a plurality of semiconductor layers having an n-type doping, and comprises an insulating layer between the plurality of semiconductor layers and the metallisation stack as dielectric; and the fourth capacitor comprises as plates the polysilicon plug and at least one of the plurality of semiconductor layers and comprises the oxide-lining as dielectric, wherein the oxide lining and the polysilicon plug form part of a lateral isolation (DTI) structure.

Abstract: An integrated electro-static discharge (ESD) device has a set of metal layers. Each metal layer in the set has one or more first-terminal metal features interleaved with one or more second-terminal metal features in a lateral direction, and at least one first-terminal metal feature in a metal layer of the set overlaps in a normal direction at least one second-terminal metal feature in an adjacent metal layer of the set. By overlapping metal features in the normal direction, capacitance can be added to the ESD device, which improves its operating characteristics, without increasing the layout size of the ESD device.

Abstract: An ESD protection device for protecting an integrated circuit against an ESD event includes a first terminal coupled to an input/output pad of the IC, a second terminal coupled to a reference or ground voltage, a silicon-controlled rectifier device having an anode connected to the first terminal and a cathode connected to the reference or ground voltage, and a pnp transistor coupled in parallel with the SCR device. The pnp transistor has an emitter coupled to the first terminal, a collector coupled to the second terminal, and a base coupled to a gate of the SCR. The pnp transistor includes a contact region formed at a first side of a substrate, the first contact region being surrounded by an STI layer formed at the first side of the substrate. An insulation structure is formed at an intersection of the first contact region and the STI layer.

Abstract: An electrostatic discharge protection device includes a substrate, first and second emitter regions disposed in the substrate, laterally spaced from one another on a side of the substrate, and having opposite conductivity types, and first and second base regions having opposite conductivity types and in which the first and second emitter regions are disposed in a thyristor arrangement, respectively. The first base region includes a buried doped layer that extends under the second base region. Each of the buried doped layer and the second base region includes a respective non-uniformity in dopant concentration profile. A spacing between the buried doped layer and the second base region at the respective non-uniformities establishes a breakdown trigger voltage for the thyristor arrangement.

Abstract: An electrostatic discharge protection device includes a substrate, first and second emitter regions disposed in the substrate, laterally spaced from one another on a side of the substrate, and having opposite conductivity types, and first and second base regions having opposite conductivity types and in which the first and second emitter regions are disposed in a thyristor arrangement, respectively. The first base region includes a buried doped layer that extends under the second base region. Each of the buried doped layer and the second base region includes a respective non-uniformity in dopant concentration profile. A spacing between the buried doped layer and the second base region at the respective non-uniformities establishes a breakdown trigger voltage for the thyristor arrangement.

Abstract: An ESD protection device for protecting an integrated circuit (IC) against an ESD event includes a first terminal coupled to an input/output pad of the IC, a second terminal coupled to a reference or ground voltage, a silicon-controlled rectifier (SCR) device having an anode connected to the first terminal and a cathode connected to the reference or ground voltage, and a pnp transistor coupled in parallel with the SCR device. The pnp transistor has an emitter coupled to the first terminal, a collector coupled to the second terminal, and a base coupled to a gate of the SCR. The pnp transistor includes a contact region formed at a first side of a substrate, the first contact region being surrounded by an STI layer formed at the first side of the substrate. An insulation structure is formed at an intersection of the first contact region and the STI layer.

Abstract: Semiconductor device and methods for making the devices includes a buried layer of a first conductivity in a substrate in which a distance between two adjacent ends can be selected to achieve a desired breakdown voltage. A deep well having a first doping concentration of a second conductivity type is implanted in an epitaxial layer above the two adjacent ends of the buried layer. A patterned doped region is formed in the deep well and extending into the epitaxial layer above and separated a distance from the two adjacent ends of the buried lay. The patterned doped region has a second doping concentration of the second conductivity type that is greater than the first doping concentration.

Abstract: A body-control-device for a bi-directional transistor, said bi-directional transistor having a first-transistor-channel-terminal, a second-transistor-channel-terminal, a transistor-control-terminal and a transistor-body-terminal. The body-control-device comprises a body-control-terminal connectable to the transistor-body-terminal of the bi-directional transistor, a first-body-channel-terminal connectable to the first-transistor-channel-terminal of the bi-directional transistor, a second-body-channel-terminal connectable to the second-transistor-channel-terminal of the bi-directional transistor, a negative-voltage-source and a switching-circuit configured to selectively provide an offset-first-circuit-path between the first-body-channel-terminal and the body-control-terminal, wherein the offset-first-circuit-path includes the negative-voltage-source such that it provides a negative voltage bias between the body-control-terminal and the first-body-channel-terminal.

Abstract: Embodiments of a transistor control device for controlling a bi-directional power transistor are disclosed. In an embodiment, a transistor control device for controlling a bi-directional power transistor includes a resistor connectable to a body terminal of the bi-directional power transistor and a transistor body switch circuit connectable to the resistor, to a drain terminal of the bi-directional power transistor, and to a source terminal of the bi-directional power transistor. The transistor body switch circuit includes switch devices and alternating current (AC) capacitive voltage dividers connected to control terminals of the switch devices. The AC capacitive voltage dividers are configured to control the switch devices to switch a voltage of the body terminal of the bi-directional power transistor as a function of a voltage between the drain terminal of the bi-directional power transistor and the source terminal of the bi-directional power transistor.

Abstract: A body-control-device for a bi-directional transistor, said bi-directional transistor having a first-transistor-channel-terminal, a second-transistor-channel-terminal, a transistor-control-terminal and a transistor-body-terminal. The body-control-device comprises a body-control-terminal connectable to the transistor-body-terminal of the bi-directional transistor, a first-body-channel-terminal connectable to the first-transistor-channel-terminal of the bi-directional transistor, a second-body-channel-terminal connectable to the second-transistor-channel-terminal of the bi-directional transistor, a negative-voltage-source and a switching-circuit configured to selectively provide an offset-first-circuit-path between the first-body-channel-terminal and the body-control-terminal, wherein the offset-first-circuit-path includes the negative-voltage-source such that it provides a negative voltage bias between the body-control-terminal and the first-body-channel-terminal.

Abstract: Semiconductor device and methods for making the devices includes a buried layer of a first conductivity in a substrate in which a distance between two adjacent ends can be selected to achieve a desired breakdown voltage. A deep well having a first doping concentration of a second conductivity type is implanted in an epitaxial layer above the two adjacent ends of the buried layer. A patterned doped region is formed in the deep well and extending into the epitaxial layer above and separated a distance from the two adjacent ends of the buried lay. The patterned doped region has a second doping concentration of the second conductivity type that is greater than the first doping concentration.

Abstract: Embodiments of a transistor control device for controlling a bi-directional power transistor are disclosed. In an embodiment, a transistor control device for controlling a bi-directional power transistor includes a resistor connectable to a body terminal of the bi-directional power transistor and a transistor body switch circuit connectable to the resistor, to a drain terminal of the bi-directional power transistor, and to a source terminal of the bi-directional power transistor. The transistor body switch circuit includes switch devices and alternating current (AC) capacitive voltage dividers connected to control terminals of the switch devices. The AC capacitive voltage dividers are configured to control the switch devices to switch a voltage of the body terminal of the bi-directional power transistor as a function of a voltage between the drain terminal of the bi-directional power transistor and the source terminal of the bi-directional power transistor.

Abstract: In one embodiment, an SCR device (41) includes a p+ wafer (417), a p? layer (416), an n+ buried layer (413) and an n? layer (414). P? wells (411,421) are formed in the n? layer (414). N+ regions (412,422) and p+ regions (415,425) are formed in the p? wells (411,421). A first ohmic contact (431) couples one n+ regions (422) to one p+ region (425). A second ohmic contact (433) couples another n+ region (412) to another p+ region (415) to provide physically and electrically symmetrical low-voltage p-n-p-n silicon controlled rectifiers. A deep isolation trench (419) surrounding the SCR device (41) and dopant concentration profiles provide a low capacitance SCR design for protecting high frequency integrated circuits from electrostatic discharges.