Abstract: Method of testing the functionality of a memory which operates at a high operating clock frequency, the method specifically having the following steps, generation of test data, copying of the generated test data at the high operating clock frequency, comparison of the copied test data with the generated test data, generation of a functionality-indicating signal for indicating the functionality of the memory if the copied test data are identical to the generated test data.

Abstract: Disclosed is a light-emitting diode chip comprising a semiconductor layer sequence suitable for emitting primary electromagnetic radiation and further comprising a converter layer that is applied to at least one main face of the semiconductor layer sequence and comprises at least one phosphor suitable for converting a portion of the primary radiation into secondary radiation, at least a portion of the secondary radiation and at least a portion of the unconverted primary radiation overlapping to form a mixed radiation with a resulting color space. The converter layer is purposefully structured to adjust a dependence of the resulting color space on viewing angle. Also disclosed is a method of making a light-emitting diode chip in which a converter layer is purposefully structured.

Abstract: Method of testing the functionality of a memory which operates at a high operating clock frequency, the method specifically having the following steps, generation of test data, copying of the generated test data at the high operating clock frequency, comparison of the copied test data with the generated test data, generation of a functionality-indicating signal for indicating the functionality of the memory if the copied test data are identical to the generated test data.

Abstract: A board includes two integrated circuits each having first terminals, second terminals, one basic configuration and one test configuration. The basic configurations contain components performing functions during normal operation of the circuits for which a particular circuit is intended. Each of the basic configurations has inputs and outputs connected to the terminals. Each of the test configurations has inputs and at least one output. Each of the inputs is connected to a respective one of the first terminals for supplying test signals to the test configuration, during a test mode of each of the circuits. The outputs are connected to the second terminals for transmitting result signals from the test configuration to the second terminals. The test and result signals are unaffected by the basic configurations during application of the test and result signals.

Abstract: An integrated circuit includes a circuit configuration for receiving a test signal and establishing an output signal as a consequence thereof. A test configuration checks if the output signal is within a given tolerance range. The test configuration has an output at which a corresponding result signal to be transmitted to outside the integrated circuit is generated when testing is performed.

Abstract: A module board in the form of a circuit board includes at least one first integrated circuit and terminal points for the at least one first integrated circuit. External terminals are provided for input/output signals. Conductor tracks have disconnectable connecting elements for connection between the external terminals and the terminal points. A second integrated circuit is disposed between the external terminals and the terminal points for differently varying the input/output signals traveling between the terminal points and the external terminals in dependence on a status of the disconnectable connecting elements.

Abstract: A monolithically integrated digital semiconductor circuit includes an address decoder, inputs connected to the address decoder for supplying external addressing signals thereto, a test decoder connected to the address decoder and connected to the external addressing signal supply inputs for directly receiving at least part of the external addressing signals, circuit parts to be addressed being connected to and controlled by the test decoder, a switch-over section connected to the test decoder for supplying a specific switch-over signal thereto causing the test decoder to be activated and causing the address decoder to be placed in a rest condition.

Abstract: Integrated dynamic write-read memory having a matrix formed of mutually identical memory cells based on MOS technology, the respective memory cells, in turn, being formed of a series arrangement of a transfer transistor and a storage capacitance, the memory cells belonging to individual columns of the matrix being connected, respectively, by a free current-carrying terminal of the transfer transistor thereof to a bit line assigned to the appertaining matrix column and being connected, respectively, by a free terminal of the storage capacitance thereof to a common fixed potential of the memory, comprising means for feeding a voltage, which causes discharge of the storage capacitance of the individual memory cells, across at least one pulsed circuit component of the matrix, for assisting in discharging the storage capacitance during an analysis of information stored in the individual memory cells.

Abstract: A signal-level converter for controlling digital MOS circuits, particularly an address-buffer circuit for dynamic MOS memories, is designed in integrable form in MOS technology and is addressed on one hand by a first supply potential and a second supply potential connected as the reference potential, and on the other hand, at a signal input by the digital control signal to be processed, and furthermore includes cross-coupled field-effect transistor pairs as well as two output terminals carrying signals inverted relative to each other for controlling the digital circuit.

Abstract: Integrated digital MOS-semiconductor circuit, including a first circuit part for generating charging and switching pulses, a second circuit part having an input connected to the first circuit part for being addressed by the pulses supplied by the first circuit part, first, second and third self-locking MOS-field effect transistors each having a source, a drain and a gate electrode, first and second capacitors having first and second terminals, the first terminal of the first capacitor being connected through the first transistor to the input of the second circuit part, the first terminal of the second capacitor being connected through the second transistor to the input of the second circuit part, a first supply potential source at reference potential, a second supply potential source different from reference potential being connected to at least one terminal of the third transistor and through the third transistor to the first terminal of the second capacitor, the second supply potential source also being con

Abstract: An integrated read-write memory matrix on a semiconductor chip with related comparators and significant address and clocking means for improved operation.