Patents by Inventor Ewan Milne
Ewan Milne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7305581Abstract: A platform for and method of computer processing to support processor failover are disclosed. A plurality of computer processors are connected to an internal communication network. A virtual local area communication network over the internal network is defined and established. Each computer processor in the virtual local area communication network has a corresponding virtual MAC address and the virtual local area network provides communication among a set of computer processors but excludes the processors from the plurality not in the defined set. A virtual storage space is defined and established with a defined correspondence to the address space of the storage network. In response to a failure by a computer processor, a computer processor from the plurality is allocated to replace the failed processor. The MAC address of the failed processor is assigned to the processor that replaces the failed processor.Type: GrantFiled: October 13, 2005Date of Patent: December 4, 2007Assignee: Egenera, Inc.Inventors: Scott Geng, Pete Manca, Paul Curtis, Ewan Milne, Max Smith, Alan Greenspan, Edward Duffy, Peter Schulter
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Publication number: 20070233809Abstract: A platform and method of deploying virtual processing areas networks are described. A plurality of computer processors are connected to an internal communication network. At least one control node is in communication with an external communication network and an external storage network has an external storage address space. The at least one control node is connected to the internal network and thereby is in communication with the plurality of computer processors. Configuration logic defines and establishes a virtual processing area network having a corresponding set of computer processors from the plurality of processors, a virtual local area communication network providing communication among the set of computer processors, and a virtual storage space with a defined correspondence to the address space of the storage network.Type: ApplicationFiled: June 6, 2007Publication date: October 4, 2007Inventors: Vern BROWNELL, Peter MANCA, Ben SPRACHMAN, Paul CURTIS, Ewan MILNE, Max SMITH, Alan GREENSPAN, Scott GENG, Dan BUSBY, Edward DUFFY, Peter SCHULTER
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Publication number: 20070233810Abstract: A platform and method of deploying virtual processing areas networks are described. A plurality of computer processors are connected to an internal communication network. At least one control node is in communication with an external communication network and an external storage network has an external storage address space. The at least one control node is connected to the internal network and thereby is in communication with the plurality of computer processors. Configuration logic defines and establishes a virtual processing area network having a corresponding set of computer processors from the plurality of processors, a virtual local area communication network providing communication among the set of computer processors, and a virtual storage space with a defined correspondence to the address space of the storage network.Type: ApplicationFiled: June 6, 2007Publication date: October 4, 2007Inventors: Vern BROWNELL, Pete MANCA, Ben SPRACHMAN, Paul CURTIS, Ewan MILNE, Max SMITH, Alan GREENSPAN, Scott GENG, Dan BUSBY, Edward DUFFY, Peter SCHULTER
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Publication number: 20070233825Abstract: A platform and method of deploying virtual processing areas networks are described. A plurality of computer processors are connected to an internal communication network. At least one control node is in communication with an external communication network and an external storage network has an external storage address space. The at least one control node is connected to the internal network and thereby is in communication with the plurality of computer processors. Configuration logic defines and establishes a virtual processing area network having a corresponding set of computer processors from the plurality of processors, a virtual local area communication network providing communication among the set of computer processors, and a virtual storage space with a defined correspondence to the address space of the storage network.Type: ApplicationFiled: June 6, 2007Publication date: October 4, 2007Inventors: Vern BROWNELL, Pete MANCA, Ben SPRACHMAN, Paul CURTIS, Ewan MILNE, Max SMITH, Alan GREENSPAN, Scott GENG, Dan BUSBY, Edward DUFFY, Peter SCHULTER
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Patent number: 7231430Abstract: A platform and method of deploying virtual processing areas networks are described. A plurality of computer processors are connected to an internal communication network. At least one control node is in communication with an external communication network and an external storage network has an external storage address space. The at least one control node is connected to the internal network and thereby is in communication with the plurality of computer processors. Configuration logic defines and establishes a virtual processing area network having a corresponding set of computer processors from the plurality of processors, a virtual local area communication network providing communication among the set of computer processors, and a virtual storage space with a defined correspondence to the address space of the storage network.Type: GrantFiled: January 4, 2002Date of Patent: June 12, 2007Assignee: Egenera, Inc.Inventors: Vern Brownell, Pete Manca, Ben Sprachman, Paul Curtis, Ewan Milne, Max Smith, Alan Greenspan, Scott Geng, Dan Busby, Edward Duffy, Peter Schulter
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Patent number: 7174390Abstract: A virtual networking system and method are disclosed. Switched Ethernet local area network semantics are provided over an underlying point to point mesh. Computer processor nodes may directly communicate via virtual interfaces over a switch fabric or they may communicate via an ethernet switch emulation. Address resolution protocol logic helps associate IP addresses with virtual interfaces while allowing computer processors to reply to ARP requests with virtual MAC addresses.Type: GrantFiled: January 4, 2002Date of Patent: February 6, 2007Assignee: Egenera, Inc.Inventors: Peter Schulter, Scott Geng, Pete Manca, Paul Curtis, Ewan Milne, Max Smith, Alan Greenspan, Edward Duffy
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Publication number: 20060107108Abstract: A platform for and method of computer processing to support processor failover are disclosed. A plurality of computer processors are connected to an internal communication network. A virtual local area communication network over the internal network is defined and established. Each computer processor in the virtual local area communication network has a corresponding virtual MAC address and the virtual local area network provides communication among a set of computer processors but excludes the processors from the plurality not in the defined set. A virtual storage space is defined and established with a defined correspondence to the address space of the storage network. In response to a failure by a computer processor, a computer processor from the plurality is allocated to replace the failed processor. The MAC address of the failed processor is assigned to the processor that replaces the failed processor.Type: ApplicationFiled: October 13, 2005Publication date: May 18, 2006Applicant: Egenera, Inc.Inventors: Scott Geng, Pete Manca, Paul Curtis, Ewan Milne, Max Smith, Alan Greenspan, Edward Duffy, Peter Schulter
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System and method for virtualizing basic input/output system (BIOS) including BIOS run time services
Patent number: 7032108Abstract: A system and method to virtualize BIOS, including run time services. A processing system has a processor, a memory system with a predefined physical address space, a storage medium, and a communication medium between the processor and the storage medium. The processing system is operable in a pre-execution environment in which a specified portion of the physical address space is used to map basic input/output system (BIOS) run time service routines. The specified portion contains RAM memory. A BIOS virtualization system includes an image of the BIOS processor-executable instructions on the storage medium and processor-executable instructions that retrieve the BIOS image from the storage medium and store the BIOS image into the RAM memory mapped into the second specified portion of physical address space.Type: GrantFiled: May 2, 2003Date of Patent: April 18, 2006Assignee: Egenera, Inc.Inventors: Justin Maynard, Ewan Milne, Robert Oakes -
Patent number: 6971044Abstract: A platform for and method of computer processing to support processor failover are disclosed. A plurality of computer processors are connected to an internal communication network. A virtual local area communication network over the internal network is defined and established. Each computer processor in the virtual local area communication network has a corresponding virtual MAC address and the virtual local area network provides communication among a set of computer processors but excludes the processors from the plurality not in the defined set. A virtual storage space is defined and established with a defined correspondence to the address space of the storage network. In response to a failure by a computer processor, a computer processor from the plurality is allocated to replace the failed processor. The MAC address of the failed processor is assigned to the processor that replaces the failed processor.Type: GrantFiled: January 4, 2002Date of Patent: November 29, 2005Assignee: Egenera, Inc.Inventors: Scott Geng, Pete Manca, Paul Curtis, Ewan Milne, Max Smith, Alan Greenspan, Edward Duffy, Peter Schulter
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System and method for virtualizing basic input/output system (BIOS) including BIOS run time services
Publication number: 20040221150Abstract: A system and method to virtualize BIOS, including run time services. A processing system has a processor, a memory system with a predefined physical address space, a storage medium, and a communication medium between the processor and the storage medium. The processing system is operable in a pre-execution environment in which a specified portion of the physical address space is used to map basic input/output system (BIOS) run time service routines. The specified portion contains RAM memory. A BIOS virtualization system includes an image of the BIOS processor-executable instructions on the storage medium and processor-executable instructions that retrieve the BIOS image from the storage medium and store the BIOS image into the RAM memory mapped into the second specified portion of physical address space.Type: ApplicationFiled: May 2, 2003Publication date: November 4, 2004Applicant: Egenera, Inc.Inventors: Justin Maynard, Ewan Milne, Robert Oakes -
Publication number: 20030130832Abstract: A virtual networking system and method are disclosed. Switched Ethernet local area network semantics are provided over an underlying point to point mesh. Computer processor nodes may directly communicate via virtual interfaces over a switch fabric or they may communicate via an ethernet switch emulation. Address resolution protocol logic helps associate IP addresses with virtual interfaces while allowing computer processors to reply to ARP requests with virtual MAC addresses.Type: ApplicationFiled: January 4, 2002Publication date: July 10, 2003Inventors: Peter Schulter, Scott Geng, Pete Manca, Paul Curtis, Ewan Milne, Max Smith, Alan Greenspan, Edward Duffy
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Publication number: 20030130833Abstract: A platform and method of deploying virtual processing areas networks are described. A plurality of computer processors are connected to an internal communication network. At least one control node is in communication with an external communication network and an external storage network has an external storage address space. The at least one control node is connected to the internal network and thereby is in communication with the plurality of computer processors. Configuration logic defines and establishes a virtual processing area network having a corresponding set of computer processors from the plurality of processors, a virtual local area communication network providing communication among the set of computer processors, and a virtual storage space with a defined correspondence to the address space of the storage network.Type: ApplicationFiled: January 4, 2002Publication date: July 10, 2003Inventors: Vern Brownell, Pete Manca, Ben Sprachman, Paul Curtis, Ewan Milne, Max Smith, Alan Greenspan, Scott Geng, Dan Busby, Edward Duffy, Peter Schulter
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Publication number: 20020156613Abstract: A platform for and method of computer processing to support processor failover are disclosed. A plurality of computer processors are connected to an internal communication network. A virtual local area communication network over the internal network is defined and established. Each computer processor in the virtual local area communication network has a corresponding virtual MAC address and the virtual local area network provides communication among a set of computer processors but excludes the processors from the plurality not in the defined set. A virtual storage space is defined and established with a defined correspondence to the address space of the storage network. In response to a failure by a computer processor, a computer processor from the plurality is allocated to replace the failed processor. The MAC address of the failed processor is assigned to the processor that replaces the failed processor.Type: ApplicationFiled: January 4, 2002Publication date: October 24, 2002Inventors: Scott Geng, Pete Manca, Paul Curtis, Ewan Milne, Max Smith, Alan Greenspan, Edward Duffy, Peter Schulter
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Publication number: 20020156612Abstract: A virtual networking system and method are disclosed. Switched Ethernet local area network semantics are provided over an underlying point to point mesh. Computer processor nodes may directly communicate via virtual interfaces over a switch fabric or they may communicate via an ethernet switch emulation. Address resolution protocol logic helps associate IP addresses with virtual interfaces while allowing computer processors to reply to ARP requests with virtual MAC addresses.Type: ApplicationFiled: January 4, 2002Publication date: October 24, 2002Inventors: Peter Schulter, Scott Geng, Pete Manca, Paul Curtis, Ewan Milne, Max Smith, Alan Greenspan, Edward Duffy