Patents by Inventor Eyal Melamed
Eyal Melamed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9917581Abstract: An electronic device comprising a first power switch connectable or connected between a first voltage source and a load is proposed. The first power switch assumes a conductive state in response to a power-on request and a non-conductive state in response to a power-off request, for energizing and deenergizing the load, so that a voltage across the first power switch tends to a positive high level when the first power switch is in the non-conductive state and to a positive low level when the first power switch is in the conductive state. The device further comprises a second power switch connectable or connected between a second voltage source and the load. The second power switch assumes a conductive state in response to the power-on request and a non-conductive state when the voltage across the first power switch is below a defined switch-off threshold lower than the high level. The second voltage source thus assists the first voltage source in powering up the load.Type: GrantFiled: May 29, 2012Date of Patent: March 13, 2018Assignee: NXP USA, Inc.Inventors: Sergey Sofer, Eyal Melamed-Kohen, Michael Priel
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Patent number: 9804224Abstract: An integrated circuit comprises a first functional unit and one or more other functional units. The first functional unit has an input for receiving data and an output for providing data. The integrated circuit tests and operates the first functional unit. Testing comprises: connecting the input of the first functional unit to the output of the first functional unit, thereby generating a loopback path from the output of the first functional unit to the input of the first functional unit; loading a test pattern onto the first functional unit; feeding a test clock signal comprising one or more clock edges, thereby prompting the first functional unit to transform the test pattern; and reading the transformed test pattern. Operating the first functional unit comprises: connecting the input of the first functional unit to an output of the other functional units; and feeding a normal clock signal to the first functional unit.Type: GrantFiled: September 22, 2014Date of Patent: October 31, 2017Assignee: NXP USA, Inc.Inventors: Eyal Melamed-Kohen, Ilan Cohen, Shlomi Sde-Paz
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Publication number: 20160084903Abstract: An integrated circuit comprises a first functional unit and one or more other functional units. The first functional unit has an input for receiving data and an output for providing data. The integrated circuit tests and operates the first functional unit. Testing comprises: connecting the input of the first functional unit to the output of the first functional unit, thereby generating a loopback path from the output of the first functional unit to the input of the first functional unit; loading a test pattern onto the first functional unit; feeding a test clock signal comprising one or more clock edges, thereby prompting the first functional unit to transform the test pattern; and reading the transformed test pattern. Operating the first functional unit comprises: connecting the input of the first functional unit to an output of the other functional units; and feeding a normal clock signal to the first functional unit.Type: ApplicationFiled: September 22, 2014Publication date: March 24, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: EYAL MELAMED-KOHEN, ILAN COHEN, SHLOMI SDE-PAZ
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Publication number: 20150084417Abstract: An electronic device comprising a first power switch connectable or connected between a first voltage source and a load is proposed. The first power switch assumes a conductive state in response to a power-on request and a non-conductive state in response to a power-off request, for energizing and deenergizing the load, so that a voltage across the first power switch tends to a positive high level when the first power switch is in the non-conductive state and to a positive low level when the first power switch is in the conductive state. The device further comprises a second power switch connectable or connected between a second voltage source and the load. The second power switch assumes a conductive state in response to the power-on request and a non-conductive state when the voltage across the first power switch is below a defined switch-off threshold lower than the high level. The second voltage source thus assists the first voltage source in powering up the load.Type: ApplicationFiled: May 29, 2012Publication date: March 26, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Sergey Sofer, Eyal Melamed-Kohen, Michael Priel
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Publication number: 20140077856Abstract: An integrated circuit device comprises a first clock signal source, arranged to provide at least one first clock signal; a second clock signal source, arranged to provide at least one second clock signal different from the at least one first clock signal; and a plurality of sequential logic cells, at least one of the plurality connected to receive, in a first mode, the at least one first clock signal or at least one clock signal derived from the at least one first clock signal, and to receive, in a second mode, the at least one second clock signal or at least one clock signal derived from the at least one second clock signal; wherein in the second mode the at least one second clock signal is adapted to the at least one of the plurality of sequential logic cells to generate in at least a portion of the integrated circuit device a current consumption when the at least one first clock signal is not a toggling signal.Type: ApplicationFiled: May 27, 2011Publication date: March 20, 2014Applicant: Freescale Semiconduction, Inc.Inventors: Sergey Sofer, Moty Groissman, Eyal Melamed-Kohen, Naom Sivam
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Patent number: 8552778Abstract: The invention relates to a duty cycle corrector for generating from an input clock signal an output clock signal having a desired duty cycle. The duty cycle corrector comprises a pulse generating stage for generating from the input clock signal a pulsed clock signal. The pulse generating stage converts rising edges of the input clock signal into pulses, each of which pulses is shorter than the desired duty cycle times the clock period. The duty cycle corrector further comprises a pulse stretching stage for generating from the pulsed clock signal the output clock signal, the pulse stretching stage delaying falling edges of the pulsed clock signal by a controlled delay.Type: GrantFiled: September 24, 2009Date of Patent: October 8, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Sergey Sofer, Eyal Melamed-Kohen, Valery Neiman
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Publication number: 20120169391Abstract: The invention relates to a duty cycle corrector for generating from an input clock signal an output clock signal having a desired duty cycle. The duty cycle corrector comprises a pulse generating stage for generating from the input clock signal a pulsed clock signal. The pulse generating stage converts rising edges of the input clock signal into pulses, each of which pulses is shorter than the desired duty cycle times the clock period. The duty cycle corrector further comprises a pulse stretching stage for generating from the pulsed clock signal the output clock signal, the pulse stretching stage delaying falling edges of the pulsed clock signal by a controlled delay.Type: ApplicationFiled: September 24, 2009Publication date: July 5, 2012Applicant: Freescale Semiconductor, Inc.Inventors: Sergey Sofer, Eyal Melamed-Kohen, Valery Neiman
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Patent number: 8081026Abstract: An integrated circuit, that includes: (i) a power gating switch, the power gating switch includes (a) an input port for receiving an input supply voltage; (b) an output port for outputting an output supply voltage; and (c) a control port for receiving a control signal that determines a difference between a value of the input supply voltage and a value of the output supply voltage; (ii) a power gated circuit, coupled to the output port of the switch, for receiving the output supply voltage; (iii) a mode indicator generator for generating a mode indicator that indicates of a desired mode of the power gated circuit; (iv) a leakage indicator generator for generating a leakage indicator that indicates of a leakage level of the power gated circuit; and (iv) a control circuit, for receiving the mode indicator and the leakage indicator, and for selecting the value of the control signal based on the mode indicator and on the leakage indicator.Type: GrantFiled: May 26, 2010Date of Patent: December 20, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Sergey Sofer, Eyal Melamed-Kohen, Valery Neiman
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Patent number: 8074195Abstract: A method for evaluating a dynamic power consumption of a block, the method includes: receiving or generating information representative of the block during a preliminary block design stage that precedes a gate level simulation of the block; estimating change probabilities of signals of internal components of the block; and evaluating a dynamic power consumption of the block in response to the change probabilities of the signals of internal components of the block.Type: GrantFiled: June 27, 2008Date of Patent: December 6, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Eyal Melamed-Kohen, Assaf Babay, Rony Bitton, Ilan Cohen
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Publication number: 20110291740Abstract: An integrated circuit, that includes: (i) a power gating switch, the power gating switch includes (a) an input port for receiving an input supply voltage; (b) an output port for outputting an output supply voltage; and (c) a control port for receiving a control signal that determines a difference between a value of the input supply voltage and a value of the output supply voltage; (ii) a power gated circuit, coupled to the output port of the switch, for receiving the output supply voltage; (iii) a mode indicator generator for generating a mode indicator that indicates of a desired mode of the power gated circuit; (iv) a leakage indicator generator for generating a leakage indicator that indicates of a leakage level of the power gated circuit; and (iv) a control circuit, for receiving the mode indicator and the leakage indicator, and for selecting the value of the control signal based on the mode indicator and on the leakage indicator.Type: ApplicationFiled: May 26, 2010Publication date: December 1, 2011Applicant: Freescale Semiconductor, Inc.Inventors: Sergey Sofer, Eyal Melamed-Kohen, Valery Neiman
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Patent number: 8009397Abstract: An eFuse (electronic fuse) circuit has a first detector for determining whether an ESD (electrostatic discharge) event occurs at a circuit pad of an integrated circuit and provides an ESD trigger signal in response thereto. A second detector detects a presence of a first power supply voltage and provides a power on signal indicating the presence of the first power supply voltage. A fuse is permitted to be programmable when no detection of the ESD event occurs and at the same time a presence of the power on signal is detected. The fuse is not permitted to be programmed when an ESD event is detected or when there is an absence of the power on signal. An array of fuses is thereby protected from inadvertent programming from an ESD event or powering up an integrated circuit.Type: GrantFiled: June 13, 2008Date of Patent: August 30, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Melanie Etherton, Michael G. Khazhinsky, Eyal Melamed-Kohen, Valery Neiman
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Patent number: 7865878Abstract: A method and apparatus for enabling an application to run from a detachable device attached to a host computer, the method comprising eliminating the usage of the registry of the computer, and using relative file paths. These modifications enable organization applications, and particularly database applications to be installed and run from a smart drive.Type: GrantFiled: July 31, 2006Date of Patent: January 4, 2011Assignee: SAP AGInventors: Aharon Weiner, Yoav Reich, Eyal Melamed, Igal Sapir, Udi Ziv
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Patent number: 7698291Abstract: A method and system for integrating user-defined objects into a business management application. A mode is selected with which to add a user-defined object in the application having a base class of objects with a base class of services. Information is received to define the user-defined object. A selection is received of at least one service from the base class of services to be associated with the user-defined object. At least one field associated with the user-defined object is received for display. Additional information may be received to define a son object of the user-defined object. Business logic may be received to be added to the application. The user-defined object and related information are registered with the application. The integrated user-defined object thereby automatically inherits the selected at least one service from the base class of services of the business management application.Type: GrantFiled: August 26, 2004Date of Patent: April 13, 2010Assignee: SAP AGInventors: Tidhar Ziv, Gilad Z. Gruber, Eyal A. Melamed
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Publication number: 20090327980Abstract: A method for evaluating a dynamic power consumption of a block, the method includes: receiving or generating information representative of the block during a preliminary block design stage that precedes a gate level simulation of the block; estimating change probabilities of signals of internal components of the block; and evaluating a dynamic power consumption of the block in response to the change probabilities of the signals of internal components of the block.Type: ApplicationFiled: June 27, 2008Publication date: December 31, 2009Inventors: Eyal Melamed-Kohen, Assaf Babay, Rony Bitton, Ilan Cohen
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Publication number: 20090310266Abstract: An eFuse (electronic fuse) circuit has a first detector for determining whether an ESD (electrostatic discharge) event occurs at a circuit pad of an integrated circuit and provides an ESD trigger signal in response thereto. A second detector detects a presence of a first power supply voltage and provides a power on signal indicating the presence of the first power supply voltage. A fuse is permitted to be programmable when no detection of the ESD event occurs and at the same time a presence of the power on signal is detected. The fuse is not permitted to be programmed when an ESD event is detected or when there is an absence of the power on signal. An array of fuses is thereby protected from inadvertent programming from an ESD event or powering up an integrated circuit.Type: ApplicationFiled: June 13, 2008Publication date: December 17, 2009Inventors: Melanie Etherton, Michael G. Khazhinsky, Eyal Melamed-Kohen, Valery Neiman
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Publication number: 20080126791Abstract: A method and apparatus for enabling an application to run from a detachable device attached to a host computer, the method comprising eliminating the usage of the registry of the computer, and using relative file paths. These modifications enable organization applications, and particularly database applications to be installed and run from a smart drive.Type: ApplicationFiled: July 31, 2006Publication date: May 29, 2008Inventors: Aharon Weiner, Yoav Reich, Eyal Melamed, Igal Sapir, Udi Ziv
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Publication number: 20060047525Abstract: A method and system for integrating user-defined objects into a business management application. A mode is selected with which to add a user-defined object in the application having a base class of objects with a base class of services. Information is received to define the user-defined object. A selection is received of at least one service from the base class of services to be associated with the user-defined object. At least one field associated with the user-defined object is received for display. Additional information may be received to define a son object of the user-defined object. Business logic may be received to be added to the application. The user-defined object and related information are registered with the application. The integrated user-defined object thereby automatically inherits the selected at least one service from the base class of services of the business management application.Type: ApplicationFiled: August 26, 2004Publication date: March 2, 2006Inventors: Tidhar Ziv, Gilad Gruber, Eyal Melamed