Abstract: The invention pertains to a method for ranking paths for power optimization of an integrated circuit design, comprising identifying a plurality of paths of the integrated circuit design, each path comprising one or more instances of electronic devices providing an instance power estimate for each instance in the identified paths providing, for each identified path, at least one weighted power estimate based on the instance power estimates for instances in the path, and providing a ranking of the paths based on the least one weighted power estimate. The invention also pertains to a corresponding computer program product.

Abstract: The invention pertains to a method for ranking paths for power optimization of an integrated circuit design, comprising identifying a plurality of paths of the integrated circuit design, each path comprising one or more instances of electronic devices providing an instance power estimate for each instance in the identified paths providing, for each identified path, at least one weighted power estimate based on the instance power estimates for instances in the path, and providing a ranking of the paths based on the least one weighted power estimate. The invention also pertains to a corresponding computer program product.

Abstract: In laying out electonic devices on a substrate the routing of nets is important in minimizing conductor area and improving performance. A method for routing of nets in an electonic device which has a plurality of clusters is disclosed which separates the intra cluster routing and the channel routing between the clusters. For the intra cluster routing a topological graph is proposed to be used for mapping a subgraph which is representative of the nodes in a net belonging to a cluster to be routed.

Abstract: In a method for generating a mapping of logical addresses to a layout of an electronic circuit structure first and second relations are established. The first relation is representative of the mapping of signal pairs to the layout and the second relation is representative of the mapping of the logical addresses to the signal pairs. Joining of the first and second relations yields a mapping table which can be used for purposes of circuit testing and design.