Abstract: A memory chip testing system includes a computer, a rheostat, a voltmeter, and a connector. The computer includes a main board, a number of memory chip interfaces mounted on the main board. The computer runs a testing software to test the stability of a memory chip under different working voltages. The connector includes an insulating substrate and a number of conductive posts. The posts with ends fixed in the insulating substrate and arranged according to the pins of the memory chip interface. The connecter is connected to the pins of one of the number of the memory chip interfaces when testing a memory chip. The rheostat and the voltmeter are electrically connected to selected conductive posts on the insulating substrate, the rheostat adjusts the work voltage of the memory chip, and the voltmeter indicates the work voltage of the memory chip.

Abstract: A debugging circuit outputs a plurality of control signals to a chip, the chip outputs a data signal according to the plurality of control signals. The debugging circuit comprises a resistor unit and an adjusting unit. The resistor unit comprises a plurality of resistors, each resistor is electrically connected to one input pin of the chip. The adjusting unit comprises a plurality of control terminals and a switch sub-unit.

Abstract: A signal test apparatus for a serial attached Small Computer System Interface (SAS) device includes an SAS female connector to be connected to the SAS device, an SAS male connector to be connected to a server, first and second pairs of subminiature version A (SMA) connectors, and first and second groups of switches. When the first pair of SMA connectors is connected to an oscillograph to test a pair of output signals from the SAS device, the second group of switches are turned on and the first group of switches are turned off to communicate the SAS device with the server. When the second pair of SMA connector is connected to the oscillograph to test another pair of output signals from the SAS device, the first group of switches are turned on and the second group of switches are turned off to communicate the SAS device with the server.

Abstract: A circuit includes first to third nodes, resistors with different resistance, capacitors with different capacitance, first switches corresponding to the same number of resistors, second switches corresponding to the same number of capacitors, and a third switch. A first terminal of each resistor is connected to the first node. A second terminal of each resistor is connected to a first terminal of a corresponding one first switch, a second terminal of each first switch is connected to the second node. A first terminal of the third switch is connected to the second terminal of each first switch. A second terminal of the third switch is connected to a first terminal of each capacitor. A second terminal of each capacitor is connected to a first terminal of a corresponding one second switch. A second terminal of each second switch is connected to the third node.

Abstract: A signal detection apparatus for a serial attached SCSI (SAS) device includes an SAS female connector to be connected to a SAS device, an SAS male connector to be connected to a system, and first to fourth pairs of subminiature version A (SMA) connectors. When the first pair of SMA connectors is connected to an oscillograph to detect a pair of output signals from the SAS device, the second and third pairs of SMA connectors connect the SAS device with the system. When the second pair of SMA connector is connected to the oscillograph to detect another pair of output signals from the SAS device, the first and fourth pairs of SMA connectors connect the SAS device with the system.

Abstract: A connector test system includes a number of adapters, a number of testers, and a motherboard. Each tester is connected to a corresponding one of the adapters. The motherboard is configured for connecting to the connector. The motherboard includes a number of pins arrayed in a 9 by 10 matrix. The pins includes a number of signal input pins and a number of grounding pins, each signal input pin is connected to a corresponding adapter.

Abstract: A method for managing memories in an electronic device includes the following steps. Detecting a change in status of all the applications installed in the electronic device, wherein the change in status of each application may include at least one start-to-run application or at least one stop-running application. If the at least one stop-running application is detected, obtaining memories occupied by the stop-running application, and powering off each obtained memory occupied by other running application. If the at least one start-to-run application is detected, determining a memory size required to enable each start-to-run application to run, determining whether a working condition of the memories needs to be changed according to the determined memory size required, and powering on the memories that are needed to enable the start-to-run application to run.

Abstract: A integrated circuit having a receiver testing function includes a signal generating circuit, a jitter output circuit, a signal mix circuit, a receiver, and an error counting circuit. The signal generating circuit outputs a reference signal to the signal mix circuit and the error counting circuit. The jitter output circuit outputs a jitter. The signal mix circuit injects the jitter into the reference signal, and outputs a testing signal that is a combination of the jitter and the reference signal. The receiver receives and then outputs the testing signal to the error counting circuit. The error counting circuit tests a performance of the receiver by determining whether a difference between a code information of the testing signal and a code information of the reference signal is within a predetermined difference range.

Abstract: A circuit includes first to third nodes, resistors with different resistance, capacitors with different capacitance, first switches corresponding to the same number of resistors, second switches corresponding to the same number of capacitors, and a third switch. A first terminal of each resistor is connected to the first node. A second terminal of each resistor is connected to a first terminal of a corresponding one first switch, a second terminal of each first switch is connected to the second node. A first terminal of the third switch is connected to the second terminal of each first switch. A second terminal of the third switch is connected to a first terminal of each capacitor. A second terminal of each capacitor is connected to a first terminal of a corresponding one second switch. A second terminal of each second switch is connected to the third node.

Abstract: In a method for managing use information of a measurement device, an operating interface of the device is locked before the device is operated. When a user starts to use the device, the method provides a login interface to verify whether the user is authorized to login the operating interface. If the user is authorized to login the operating interface, the operating interface is unlocked and the method records first information of starting to operate the device. After finishing the operation or when an elapsed time of the device not in use is greater than a predetermined time, the method controls the user to log out the operating interface, records second information of finishing the operation, and the operating interface is locked. The first information and the second information are saved in a text file.

Abstract: A measuring apparatus includes a first connector connected to a storage controller through a second connector of a motherboard. A control circuit receives voltage signals from the storage controller and converts the voltage signals to hard disk drive (HDD) power signals. A detecting circuit includes an AND gate and first to fourth resistors. A first input terminal of the AND gate is grounded through the first resistor and connected to the control circuit through the second resistor. A second input terminal of the AND gate is grounded through the third resistor and connected to the control circuit through the fourth resistor. An output terminal of the AND gate is connected to a measuring pin of the first connector. The AND gate receives the HDD power signals and outputs a power good (PWG) signal to the measuring pin of the first connector to be measured.

Abstract: A signal test apparatus for a serial attached Small Computer System Interface (SAS) device includes an SAS female connector to be connected to the SAS device, an SAS male connector to be connected to a server, first and second pairs of subminiature version A (SMA) connectors, and first and second groups of switches. When the first pair of SMA connectors is connected to an oscillograph to test a pair of output signals from the SAS device, the second group of switches are turned on and the first group of switches are turned off to communicate the SAS device with the server. When the second pair of SMA connector is connected to the oscillograph to test another pair of output signals from the SAS device, the first group of switches are turned on and the second group of switches are turned off to communicate the SAS device with the server.

Abstract: A bracket is used to support a motherboard. The bracket includes a framework, a first supporting element, and a second supporting element. The framework includes a front bar, a back bar, and two side bars, corporately bounding a receiving space. The first and second supporting elements are received in the receiving space and connected to the two side bars. A number of through holes corresponding to a number of through holes of the motherboard are defined in the framework, the first supporting element, and the second supporting elements to fix the motherboard on the bracket via a plurality of screw pillars extending through the plurality of through holes of the bracket and the plurality of through holes of the motherboard.

Abstract: An assistant test circuit board for assisting a tester to test a number of signal welds and a number of ground welds on a printed circuit board includes a ground pin, a same number of ground pads as ground welds, test pads, and a same number of test pins as signal welds. Each test pad and each ground pad located on a fist side of the circuit board are soldered to the corresponding signal weld and ground weld, while the test pins and the ground pin are connected to the tester.

Abstract: A serial attached small computer system interface (SCSI) (SAS) interface output signal detecting apparatus includes an SAS female connector, an SAS male connector, and two subminiature version A (SMA) connectors. Each of the SAS female and male connectors includes first and second groups of data pins and a group of power pins. The power pins of the SAS female connector are connected to the power pins of the SAS male connector. The SMA connectors are connected to two data output pins of the second or first group of data pins of the SAS female connector in response to the first group of data pins of the SAS female connector being connected to the first group of data pins of the SAS male connector or the second group of data pins of the SAS female connector being connected to the second group of data pins of the SAS male connector.

Abstract: A signal detection apparatus for a serial attached SCSI (SAS) device includes an SAS female connector to be connected to a SAS device, an SAS male connector to be connected to a system, and first to fourth pairs of subminiature version A (SMA) connectors. When the first pair of SMA connectors is connected to an oscillograph to detect a pair of output signals from the SAS device, the second and third pairs of SMA connectors connect the SAS device with the system. When the second pair of SMA connector is connected to the oscillograph to detect another pair of output signals from the SAS device, the first and fourth pairs of SMA connectors connect the SAS device with the system.

Abstract: A connection apparatus used to connect a connector to a test apparatus includes a main board, a first connector, and a number of second connectors. The main board includes a number of pins arrayed a 9*10 matrix, the nine lines defined as A-I, the ten rows defined as 1-10. The second connectors are respectively connected to the pins A5, B5, D5, E5, G5, H5, B6, C6, E6, F6, H6, and I6 of the main board. The pins of main board in the 1-6 rows, the 3-8 rows and the 5-10 rows are respectively connected to the connector to be tested by the first connector. Signal transmission of the connector is input to the circuit board and output to the test apparatus by the second connectors.

Abstract: A measuring apparatus includes a first connector connected to a storage controller through a second connector of a motherboard. A control circuit receives voltage signals from the storage controller and converts the voltage signals to hard disk drive (HDD) power signals. A detecting circuit includes an AND gate and first to fourth resistors. A first input terminal of the AND gate is grounded through the first resistor and connected to the control circuit through the second resistor. A second input terminal of the AND gate is grounded through the third resistor and connected to the control circuit through the fourth resistor. An output terminal of the AND gate is connected to a measuring pin of the first connector. The AND gate receives the HDD power signals and outputs a power good (PWG) signal to the measuring pin of the first connector to be measured.

Abstract: A connector test system includes a number of adapters, a number of testers, and a motherboard. Each tester is connected to a corresponding one of the adapters. The motherboard is configured for connecting to the connector. The motherboard includes a number of pins arrayed in a 9 by 10 matrix. The pins includes a number of signal input pins and a number of grounding pins, each signal input pin is connected to a corresponding adapter.

Abstract: A test bracket for testing a circuit board includes a base, two connection pieces, and a supporting member for supporting the circuit board. The base includes a board and two posts extending up from the board. The supporting member is pivotably installed between the posts. First ends of the connection pieces are respectively slidably connected to the posts, and second ends of the connection pieces opposite to the first ends are respectively pivotably connected to opposite sides of the supporting member.