Patents by Inventor Fabio M. Chiussi

Fabio M. Chiussi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030142624
    Abstract: A scheduling apparatus flexibly integrates guaranteed-bandwidth (GB) and best-effort (BE) flows and comprises a combination of a primary weighted-round-robin (WRR) scheduler (PWS) and a secondary WRR scheduler (SWS). The PWS distributes service to the individual GB flows and determines the amount of service that the BE flow aggregate should receive during each frame. The SWS takes care of fairly distributing the service share of the BE aggregate over the individual BE flows. The scheduling apparatus divides the service frame in two subframes. In the first subframe, the PWS fulfills the bandwidth requirements of the GB flows. In the second subframe, the SWS distributes fair service to the BE flows. For each frame, the duration depends on the amount of bandwidth allocated to the GB flows and on the number of GB flows that are backlogged at the beginning of the frame. The amount of bandwidth globally available to BE flows (i.e.
    Type: Application
    Filed: November 13, 2001
    Publication date: July 31, 2003
    Inventors: Fabio M. Chiussi, Kevin D. Drucker, Andrea Francini
  • Patent number: 6532213
    Abstract: A system is disclosed that services a plurality of queues associated with respective data connections in a packet communication network such that the system guarantees data transfer delays between the data source and the destination of each data connection. This is achieved in two stages. The first stage shapes the traffic of each connection such that it conforms to a specified envelope. The second stage associates timestamps with the packets released by the first stage and chooses for transmission from among them the one with the smallest timestamp. Both stages are associated with a discrete set of delay classes. The first stage employs one shaping structure per delay class. Each shaping structure in turn supports a discrete set of rates and employs a FIFO of connections per supported rate. A connection may move between FIFOs corresponding to different rates as its rate requirement changes.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: March 11, 2003
    Assignee: Agere Systems Inc.
    Inventors: Fabio M. Chiussi, Vijay Sivaraman