Abstract: Packets or frames of data may be compressed, encrypted/decrypted, filtered, classified, searched or subjected to other deep-packet processing operations before being distributed through the internet. The microprocessor system and method of the present invention provide for the orderly processing of such data packets without disrupting or changing the sequence in which the data is intended to be transmitted to its destination. This is achieved by receiving frames into an input buffer for processing. Associated with this input buffer is a unit for determining the operation to be performed on each frame. An arbitrator assigns each frame to a processing core engine. An output buffer collects the processed frames, and a sequencer forwards the processed frames from the output buffer to their destination in the same order as received by the input/output buffer. Maintaining the sequence of data transmission is particularly useful in voice transmission, such as videos and movies.

Abstract: A method for performing a lookup for a packet in a computer network are disclosed. The packet includes a header. The method includes providing a parser, providing a lookup engine coupled with the parser, and providing a processor coupled with the lookup engine. The parser is for parsing the packet for the header prior to receipt of the packet being completed. The lookup engine performs a lookup for the header and returns a resultant. In one aspect, the lookup includes performing a local lookup of a cache that includes resultants of previous lookups. The processor processes the resultant.

Abstract: Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a four-entry calendar structure provides for rate-limited weighted best effort scheduling. Each of a plurality of different flows has associated schedule control blocks. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a rate limit according to the bandwidth priority of the flow to which the corresponding packet belongs.

Abstract: A system for reducing latency in a host Ethernet adapter (HEA) includes the following. First, the HEA receives a packet with an internet protocol (IP) header and data in the HEA. The HEA parses a connection identifier from the IP header and accesses a negative cache in the HEA to determine if the connection identifier is not in a memory external to the HEA. The HEA applies a default treatment to the packet if the connection identifier is not in the memory, thereby reducing latency by decreasing access to the memory.

Abstract: Systems and methods for adaptively mapping system memory address bits into an instruction tag and an index into the cache are disclosed. More particularly, hardware and software are disclosed for observing collisions that occur for a given mapping of system memory bits into a tag and an index. Based on the observations, an optimal mapping may be determined that minimizes collisions.

Abstract: A system for performing a lookup for a packet in a computer network are disclosed. The packet includes a header. The system includes a parser, a lookup engine coupled with the parser, and a processor coupled with the lookup engine. The parser parses the packet for the header prior to receipt of the packet being completed. The lookup engine performs a lookup for the header and returns a resultant. In one aspect, the lookup includes performing a local lookup of a cache that includes resultants of previous lookups. The processor processes the resultant.

Abstract: A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.

Abstract: A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

Abstract: Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.

Abstract: Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one” or “zero” and indicates when the data buffer having the last bit is transmitted. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

Abstract: Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.

Abstract: A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.

Abstract: Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

Abstract: Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first: match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.

Abstract: Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

Abstract: Packets or frames of data may be compressed, encrypted/decrypted, filtered, classified, searched or subjected to other deep-packet processing operations before being distributed through the internet. The microprocessor system and method of the present invention provide for the orderly processing of such data packets without disrupting or changing the sequence in which the data is intended to be transmitted to its destination. This is achieved by receiving frames into an input buffer for processing. Associated with this input buffer is a unit for determining the operation to be performed on each frame. An arbitrator assigns each frame to a processing core engine. An output buffer collects the processed frames, and a sequencer forwards the processed frames from the output buffer to their destination in the same order as received by the input/output buffer. Maintaining the sequence of data transmission is particularly useful in voice transmission, such as videos and movies.

Abstract: A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. A system for allowing peak bursts based on a system of credits and charges is taught along limits on such peak bursts. Also taught is a system for preventing a flow's disconnection and reconnection to the queues from allowing it to unfairly achieve an improved position.