Abstract: A phase-locked loop (PLL) device includes synchronization means suitable for synchronizing a frequency-converted signal produced by a frequency divider of the PLL device, with a reference signal supplied to the PLL device. A time duration of a frequency/phase lock acquisition step which is performed upon starting an operation of the PLL device can be reduced. In addition, when operating several PLL devices simultaneously, the synchronization units allow recovering target values for phase differences that exist between the respective frequency-converted signals of the PLL devices. To this end, synchronization is requested at a same time for all the PLL devices after they are all running in locked state.

Abstract: A phase-locked loop (PLL) device includes synchronization means suitable for synchronizing a frequency-converted signal produced by a frequency divider of the PLL device, with a reference signal supplied to the PLL device. A time duration of a frequency/phase lock acquisition step which is performed upon starting an operation of the PLL device can be reduced. In addition, when operating several PLL devices simultaneously, the synchronization units allow recovering target values for phase differences that exist between the respective frequency-converted signals of the PLL devices. To this end, synchronization is requested at a same time for all the PLL devices after they are all running in locked state.

Abstract: A system in accordance with the present invention may include a phase-locked loop circuit, comprising a first input signal oscillating at a reference frequency, a second input signal received from a voltage-controlled oscillator (VCO) after passing through an N-divider, a phase detector and charge-pump, the phase detector comparing a phase of the first input signal and a phase of the second input signal, a loop filter in series with the phase detector and charge-pump, the loop filter having an integrator, a pole zero, and a post-filter, and a buffer in parallel with the integrator and in series with the post-filter, the buffer receiving an output signal from the integrator and isolating the integrator from an input impedance of the post-filter, and the buffer having a multiplexer for selecting between a plus and minus level shift signal, wherein the VCO is in series with the loop filter and the N-divider, and the VCO is configured to receive a tuning voltage signal from the loop filter.

Abstract: A system in accordance with the present invention may include a phase-locked loop circuit, comprising a first input signal oscillating at a reference frequency, a second input signal received from a voltage-controlled oscillator (VCO) after passing through an N-divider, a phase detector and charge-pump, the phase detector comparing a phase of the first input signal and a phase of the second input signal, a loop filter in series with the phase detector and charge-pump, the loop filter having an integrator, a pole zero, and a post-filter, and a buffer in parallel with the integrator and in series with the post-filter, the buffer receiving an output signal from the integrator and isolating the integrator from an input impedance of the post-filter, and the buffer having a multiplexer for selecting between a plus and minus level shift signal, wherein the VCO is in series with the loop filter and the N-divider, and the VCO is configured to receive a tuning voltage signal from the loop filter.

Abstract: A mixer circuit with image frequency rejection comprising a quadrature phase divider (30, 30?) presenting an input connected to the input (Fi) of the mixer circuit and two outputs respectively delivering two signals in phase quadrature which are applied respectively to two simple mixers (31, 32; 31?, 32?), said mixer circuit comprising a quadrature phase and frequency divider (33, 33?) having a frequency division ratio and presenting two inputs respectively connected to the respective outputs of the two simple mixers (31, 32; 31?, 32?) and a first output delivering a first output signal (Fo) of the mixer circuit, which signal is applied to the inputs of the two simple mixers.

Abstract: A mixer circuit with image frequency rejection comprising a quadrature phase divider (30, 30′) presenting an input connected to the input (Fi) of the mixer circuit and two outputs respectively delivering two signals in phase quadrature which are applied respectively to two simple mixers (31, 32; 31′, 32′), said mixer circuit comprising a quadrature phase and frequency divider (33, 33′) having a frequency division ratio and presenting two inputs respectively connected to the respective outputs of the two simple mixers (31, 32; 31′, 32′) and a first output delivering a first output signal (Fo) of the mixer circuit, which signal is applied to the inputs of the two simple mixers.

Abstract: A frequency synthesizer comprising a phase-locked loop (10) and comprising: a frequency divider (14) having integral dividing ratios, a sigma-delta modulator (30) connected to the frequency divider for obtaining a resulting mean dividing ratio having a fractional component, the modulator having an input for an adjusting instruction, and at least a frequency divider (100) having a fixed fractional dividing ratio, and means (120, 40) for activating the divider having a fractional dividing ratio when the fractional component (k) of the mean dividing ratio is contained in at least a given value range, and for modifying the adjusting instruction in corresponding manner.

Abstract: The present invention relates a frequency synthesizer comprising in a phase-locked loop: a phase-frequency comparator (16) connected to a reference frequency source (20), at least a voltage-controlled oscillator (12) and a fractional frequency divider (14) suitable for producing a mean dividing ratio having an integral component and a fractional component. According to the invention, the oscillator comprises a plurality of oscillator stages which have different center frequencies, and the synthesizer further includes means for selecting an oscillator stage as a function of the integral component of the mean dividing ratio. Application to portable telephones.

Abstract: A frequency synthesizer comprising a phase-locked loop that includes a phase-frequency comparator (16), at least a voltage-controlled oscillator (12) associated with a selection apparatus (50, 80, 82) of an oscillation frequency band, and a frequency divider (14) connected between the oscillator and the comparator. A voltage source proper (90) is connected to the selection apparatus for supplying it with a control voltage proper.

Abstract: An integrated circuit includes at least an inductive element and an active region which may include resistive, capacitive and semiconductor elements. The inductive element and part of the active region are superimposed. The integrated circuit has a screen for insulating the active region with respect to an electromagnetic field that the inductive element develops. The screen allows the implementation of inductive elements having high quality factors in integrated circuits of reduced size and in which the electromagnetic interactions between the inductive elements and the other elements are reduced.

Abstract: A frequency synthesizer including a phase-locked loop (10), which phase-locked loop (10) comprises:

Abstract: The invention relates to a frequency synthesizer comprising in a phase-locked loop:

Abstract: A frequency synthesizer comprising a phase-locked loop (10) and comprising:

Abstract: The present invention relates a frequency synthesizer comprising in a phase-locked loop:

Abstract: The present invention relates to an integrated circuit comprising a series of conducting layers (1) . . . (6), separated in pairs by insulating layers, including a capacitive element CF formed by a stack of conducting layers cut out of the conducting layers. According to the invention, the capacitive element CF comprises as many conductive plates as the integrated circuit has conducting layers. The invention enables to maximize the reduction of the influence of each of its manufacturing steps on the real value of the capacitive element CF.

Abstract: The invention relates to an oscillator OSC intended to provide an output signal having a frequency which is variable as a function of a tuning voltage Vtun. The oscillator OSC includes a passive part having two series-arranged variable capacitances Cs, biased by the tuning voltage Vtun, and connected to a power supply VCC via two inductances Lext, and an active part having a first transistor T1 and a second transistor T2 whose collectors are connected to the output terminals C1 and C2 of the passive part, the base of one transistor being connected to the collector of the other transistor via a coupling capacitor Cfb. According to the invention, the passive part includes two high-pass filters, each being inserted between one of the output terminals S1 or S2 and one of the variable capacitances Cs, which allows a reduction of the active part's sensitivity to low-frequency noise.