Abstract: The present invention relates to a device having a central processing unit, RAM memory and at least two hardware elementary operations, using registers of greater size than the one of the central processing unit, said device being such that construction of at least one part of RAM memory is managed only by the hardware elementary operations, hardware elementary operations themselves and masking of inputs/outputs/intermediary data are monitored by software instructions, said software instructions being able to address different cryptographic functionalities using said hardware elementary operations according to several ways depending on each concerned functionality, said software instructions being further able to address several levels of security in the execution of the different functionalities.

Abstract: A processing unit executes a sensitive computation using multiple different and independent branches that each necessitate a given number of processing unit time units to be executed. Each execution of a sensitive computation includes: generating at least as many identifiers as the number of branches; associating each identifier to a unique branch; generating a random permutation of identifiers, wherein the number of occurrences of each identifier in the permutation is at least equal to the number of processing unit time units in the shortest of the branches; successively determining, wherein the determining includes processing each identifier in the random permutation, which branch to execute by each successive processing unit time units according to the identifier in the random permutation; and for each identifier of the random permutation, executing a processing unit time unit for the branch determined according to the identifier in the random permutation.

Abstract: The present invention relates to a device having a central processing unit, RAM memory and at least two hardware elementary operations, using registers of greater size than the one of the central processing unit, said device being such that construction of at least one part of RAM memory is managed only by the hardware elementary operations, hardware elementary operations themselves and masking of inputs/outputs/intermediary data are monitored by software instructions, said software instructions being able to address different cryptographic functionalities using said hardware elementary operations according to several ways depending on each concerned functionality, said software instructions being further able to address several levels of security in the execution of the different functionalities.

Abstract: The present invention relates to a method to execute by a processing unit a sensitive computation using multiple different and independent branches each necessitating a given number of processing unit time units to be executed, characterized in that it comprises the following steps of, at each execution of a sensitive computation: generating at least as many identifiers as the number of branches, associating each identifier to a unique branch, generating a random permutation of identifiers, the number of occurrences of each identifier in the permutation being at least equal to the number of central processing unit time units in the shortest of the branches, by processing each identifier in the random permutation, determining successively the branch to execute by each successive central processing unit time units according to the identifier value, for each identifier of the random permutation, executing a central processing unit time unit for the branch determined according to the identifier value.

Abstract: The present invention relates to cryptographic method that are resistant to fault injection attacks, to protect the confidentiality and the integrity of secret keys. For that, the invention describes a method to protect a key hardware register against fault attack, this register being inside an hardware block cipher BC embedded inside an electronic component, said component containing stored inside a memory area a cryptographic key K, characterized in that it comprises following steps: A.) loading the key Kram inside said register; B.) computing a value X such as K=BC(K,X); C.) after at least one sensitive operation, computing a value V such as V=BC(K,X); D.) matching the value V with the key Kram value stored in the memory area; E.) if the matching is not ok detecting that a fault occurs.

Abstract: The present invention relates to cryptographic method that are resistant to fault injection attacks, to protect the confidentiality and the integrity of secret keys. For that, the invention describes a method to protect a key hardware register against fault attack, this register being inside an hardware block cipher BC embedded inside an electronic component, said component containing stored inside a memory area a cryptographic key K, characterized in that it comprises following steps: A.) loading the key Kram inside said register; B.) computing a value X such as K=BC(K,X); C.) after at least one sensitive operation, computing a value V such as V=BC(K,X); D.) matching the value V with the key Kram value stored in the memory area; E.) if the matching is not ok detecting that a fault occurs.

Abstract: The invention relates to a process to make secure a personal portable object comprising a body of the personal portable object, a microchip, a printed image and a device to enable said personal portable object to communicate with an entity external to the device. The process includes using an image file and an insertion algorithm to generate an image feature vector Vsi(num), storing the image feature vector Vsi(num) in the microchip, using the printed image obtained by a scanning device to generate an image feature vector Vsi(dig), and using a read-back algorithm to match the image feature vector Vsi(num) and the image feature vector Vsi(dig).

Abstract: The invention relates to a process to make secure a personal portable object comprising a body of the personal portable object, a microchip, a printed image and a device to enable said personal portable object to communicate with an entity external to the device. The process includes using an image file and an insertion algorithm to generate an image feature vector Vsi(num), storing the image feature vector Vsi(num) in the microchip, using the printed image obtained by a scanning device to generate an image feature vector Vsi(dig), and using a read-back algorithm to match the image feature vector Vsi(num) and the image feature vector Vsi(dig).

Abstract: The invention relates to a process to make secure a personal portable object comprising a body of the personal portable object, a microchip, a printed image and a device to enable said personal portable object to communicate with an entity external to the device. The process includes using an image file and an insertion algorithm to generate an image feature vector Vsi(num), storing the image feature vector Vsi(num) in the microchip, using the printed image obtained by a scanning device to generate an image feature vector Vsi(dig), and using a read-back algorithm to match the image feature vector Vsi(num) and the image feature vector Vsi(dig).

Abstract: The invention relates to a process to make secure a personal portable object comprising a body of the personal portable object, a microchip, a printed image and a device to enable said personal portable object to communicate with an entity external to the device. The process includes using an image file and an insertion algorithm to generate an image feature vector Vsi(num), storing the image feature vector Vsi(num) in the microchip, using the printed image obtained by a scanning device to generate an image feature vector Vsi(dig), and using a read-back algorithm to match the image feature vector Vsi(num) and the image feature vector Vsi(dig).