Patents by Inventor Fabrice Romain
Fabrice Romain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11922133Abstract: A method includes processing, by an arithmetic and logic unit of a processor, masked data, and keeping, by the arithmetic and logic unit of the processor, the masked data masked throughout their processing by the arithmetic and logic unit. A processor includes an arithmetic and logic unit configured to keep masked data masked throughout processing of the masked data in the arithmetic and logic unit.Type: GrantFiled: September 30, 2020Date of Patent: March 5, 2024Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SASInventors: Rene Peyrard, Fabrice Romain, Jean-Michel Derien, Christophe Eichwald
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Patent number: 11762633Abstract: The present disclosure relates to a circuit and method for determining a sign indicator bit of a binary datum including a step for processing of the binary datum masked with a masking operation, and not including any processing step of the binary datum.Type: GrantFiled: September 30, 2020Date of Patent: September 19, 2023Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SASInventors: Rene Peyrard, Fabrice Romain
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Patent number: 11742050Abstract: A method for detecting a reading error of a datum in memory. A binary word which is representative of the datum and an error correcting or detecting code is read by: reading a first part of the binary word stored at a first address in a first memory circuit; and reading a second part of the binary word stored at a second address in a second memory circuit. The first and second parts read from the first and second memory circuits, respectively, are concatenated to form a read binary word. The datum is then obtained by removing the error correcting or detecting code from the read binary word. A new error correcting or detecting code is calculated from the obtained datum and compared to the removed error correcting or detecting code to detect error in the obtained datum.Type: GrantFiled: June 13, 2022Date of Patent: August 29, 2023Assignee: STMicroelectronics (Rousset) SASInventors: Fabrice Romain, Mathieu Lisart
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Patent number: 11714604Abstract: An embodiment method for determining a carry digit indicator bit of a first binary datum includes a step for processing of the first binary datum masked by a masking operation, and not including any processing step of the first binary datum.Type: GrantFiled: September 30, 2020Date of Patent: August 1, 2023Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS (GPENOBLE 2) SASInventors: Rene Peyrard, Fabrice Romain
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Patent number: 11640844Abstract: A method for detecting a writing error of a datum in memory includes: storing at least two parts of equal size of a binary word representative of said datum at the same address in at least two identical memory circuits, and comparing internal control signals of the two memory circuits to determine existence of the writing error.Type: GrantFiled: September 2, 2020Date of Patent: May 2, 2023Assignee: STMicroelectronics (Rousset) SASInventors: Fabrice Romain, Mathieu Lisart
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Patent number: 11575402Abstract: The present description concerns an electronic device including: a modulator-demodulator circuit; a first integrated circuit implementing a first subscriber identification module; and at least one second integrated circuit intended to implement a second subscriber identification module, wherein a sequencing terminal of the first circuit and a sequencing terminal of the second circuit are connected to a same sequencing terminal of the modulator-demodulator circuit.Type: GrantFiled: October 27, 2021Date of Patent: February 7, 2023Assignee: STMicroelectronics (Rousset) SASInventor: Fabrice Romain
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Publication number: 20220391171Abstract: In an embodiment, after a first phase of multiplication, in an electronic multiplication circuit, of a first operand by a second operand leading to a successive delivery of least significant words of the result of the first multiplication, a second multiplication, of the first operand by a supplementary operand is implemented in the electronic multiplication circuit, during a second phase of multiplication. The supplementary operands are not all identical.Type: ApplicationFiled: May 13, 2022Publication date: December 8, 2022Inventors: Fabrice Romain, Fabien Journet
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Patent number: 11509332Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.Type: GrantFiled: August 4, 2021Date of Patent: November 22, 2022Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Alps) SASInventors: Fabrice Romain, Mathieu Lisart, Patrick Arnould
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Publication number: 20220310192Abstract: A method for detecting a reading error of a datum in memory. A binary word which is representative of the datum and an error correcting or detecting code is read by: reading a first part of the binary word stored at a first address in a first memory circuit; and reading a second part of the binary word stored at a second address in a second memory circuit. The first and second parts read from the first and second memory circuits, respectively, are concatenated to form a read binary word. The datum is then obtained by removing the error correcting or detecting code from the read binary word. A new error correcting or detecting code is calculated from the obtained datum and compared to the removed error correcting or detecting code to detect error in the obtained datum.Type: ApplicationFiled: June 13, 2022Publication date: September 29, 2022Applicant: STMicroelectronics (Rousset) SASInventors: Fabrice ROMAIN, Mathieu LISART
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Publication number: 20220190862Abstract: The present description concerns an electronic device including: a modulator-demodulator circuit; a first integrated circuit implementing a first subscriber identification module; and at least one second integrated circuit intended to implement a second subscriber identification module, wherein a sequencing terminal of the first circuit and a sequencing terminal of the second circuit are connected to a same sequencing terminal of the modulator-demodulator circuit.Type: ApplicationFiled: October 27, 2021Publication date: June 16, 2022Inventor: Fabrice Romain
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Publication number: 20220069811Abstract: An output potential level among two first levels is delivered according to an input level among two second levels. The output potential level is delivered at a first node connecting together first and second transistors electrically in series between two second nodes of application of the first levels. A first DC voltage defining a high limit for the control voltage of the first transistor is delivered by a first voltage generator powered by one of the second nodes. A second DC voltage defining a high limit for the control voltage of the second transistor is delivered by a second voltage generator controlled by a value representative of the first voltage and powered between the second nodes.Type: ApplicationFiled: August 26, 2021Publication date: March 3, 2022Applicant: STMicroelectronics (Grenoble 2) SASInventors: Denis COTTIN, Fabrice ROMAIN
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Publication number: 20210367619Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.Type: ApplicationFiled: August 4, 2021Publication date: November 25, 2021Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Alps) SASInventors: Fabrice ROMAIN, Mathieu LISART, Patrick ARNOULD
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Patent number: 11115061Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.Type: GrantFiled: September 2, 2020Date of Patent: September 7, 2021Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Alps) SASInventors: Fabrice Romain, Mathieu Lisart, Patrick Arnould
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Publication number: 20210109713Abstract: The present disclosure relates to a device and method for processing masked binary data values, comprising extracting and inserting a first part of a first masked binary data value in a second masked binary data value, in which the first and second masked binary data values stay masked throughout all of the processing.Type: ApplicationFiled: September 30, 2020Publication date: April 15, 2021Inventors: Rene Peyrard, Fabrice Romain
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Publication number: 20210109711Abstract: An embodiment relates to a method for processing masked data using a processor comprising an arithmetic and logic unit, in which the masked data remain masked during their processing in the arithmetic and logic unit.Type: ApplicationFiled: September 30, 2020Publication date: April 15, 2021Inventors: Rene Peyrard, Fabrice Romain, Jean-Michel Derien, Christophe Eichwald
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Publication number: 20210109714Abstract: The present disclosure relates to a circuit and method for determining a sign indicator bit of a binary datum including a step for processing of the binary datum masked with a masking operation, and not including any processing step of the binary datum.Type: ApplicationFiled: September 30, 2020Publication date: April 15, 2021Inventors: Rene Peyrard, Fabrice Romain
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Publication number: 20210109708Abstract: An embodiment method for determining a carry digit indicator bit of a first binary datum includes a step for processing of the first binary datum masked by a masking operation, and not including any processing step of the first binary datum.Type: ApplicationFiled: September 30, 2020Publication date: April 15, 2021Inventors: Rene Peyrard, Fabrice Romain
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Publication number: 20210067177Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.Type: ApplicationFiled: September 2, 2020Publication date: March 4, 2021Applicants: STMicroelectronics (Rousset) SAS, STMicroelectronics (Alps) SASInventors: Fabrice ROMAIN, Mathieu LISART, Patrick Arnould
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Publication number: 20210065834Abstract: A method for detecting a writing error of a datum in memory includes: storing at least two parts of equal size of a binary word representative of said datum at the same address in at least two identical memory circuits, and comparing internal control signals of the two memory circuits to determine existence of the writing error.Type: ApplicationFiled: September 2, 2020Publication date: March 4, 2021Applicant: STMicroelectronics (Rousset) SASInventors: Fabrice ROMAIN, Mathieu LISART
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Patent number: 10783091Abstract: The present disclosure concerns a memory access control system comprising: a processing device capable of operating in a plurality of operating modes, and of accessing a memory using a plurality of address aliases; and a verification circuit configured: to receive, in relation with a first read operation of a first memory location in the memory, an indication of a first of said plurality of address aliases associated with the first read operation; to verify that a current operating mode of the processing device permits the processing device to access the memory using the first address alias; to receive, during the first read operation, a first marker stored at the first memory location; and to verify, based on the first marker and on the first address alias, that the processing device is permitted to access the first memory location.Type: GrantFiled: September 13, 2018Date of Patent: September 22, 2020Assignee: STMICROELECTRONICS (ROUSSET) SASInventor: Fabrice Romain