Patents by Inventor Fabrizio Fausto Renzo Toia
Fabrizio Fausto Renzo Toia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220384585Abstract: An integrated electronic circuit including: a dielectric body delimited by a front surface; A top conductive region of an integrated electronic circuit extend within a dielectric body having a front surface. A passivation structure including a bottom portion and a top portion laterally delimits an opening. The bottom portion extends on the front surface, and the top portion extends on the bottom portion. A field plate includes an internal portion and an external portion. The internal portion is located within the opening and extends on the top portion of the passivation structure. The external portion extends laterally with respect to the top portion of the passivation structure and contacts at a bottom one of: the dielectric body or the bottom portion of the passivation structure. The opening and the external portion are arranged on opposite sides of the top portion of the passivation structure.Type: ApplicationFiled: May 25, 2022Publication date: December 1, 2022Applicant: STMicroelectronics S.r.l.Inventors: Elisabetta PIZZI, Dario RIPAMONTI, Matteo PATELMO, Fabrizio Fausto Renzo TOIA, Simone Dario MARIANI
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Patent number: 11469136Abstract: A technique to make silicon oxide regions from porous silicon and related semiconductor structures is disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.Type: GrantFiled: August 24, 2020Date of Patent: October 11, 2022Assignee: STMICROELECTRONICS S.r.l.Inventors: Simone Dario Mariani, Fabrizio Fausto Renzo Toia, Marco Sambi, Davide Giuseppe Patti, Marco Morelli, Giuseppe Barillaro
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Patent number: 11302471Abstract: An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding.Type: GrantFiled: January 16, 2020Date of Patent: April 12, 2022Assignee: STMicroelectronics S.r.l.Inventors: Vincenzo Palumbo, Gabriella Ghidini, Enzo Carollo, Fabrizio Fausto Renzo Toia
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Publication number: 20210143286Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.Type: ApplicationFiled: January 20, 2021Publication date: May 13, 2021Applicant: STMicroelectronics S.r.l.Inventors: Flavio Francesco VILLA, Marco MORELLI, Marco MARCHESI, Simone Dario MARIANI, Fabrizio Fausto Renzo TOIA
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Patent number: 10930799Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.Type: GrantFiled: January 14, 2019Date of Patent: February 23, 2021Assignee: STMicroelectronics S.r.l.Inventors: Flavio Francesco Villa, Marco Morelli, Marco Marchesi, Simone Dario Mariani, Fabrizio Fausto Renzo Toia
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Publication number: 20200395240Abstract: A technique to make silicon oxide regions from porous silicon and related semiconductor structures is disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.Type: ApplicationFiled: August 24, 2020Publication date: December 17, 2020Inventors: Simone Dario MARIANI, Fabrizio Fausto Renzo TOIA, Marco SAMBI, Davide Giuseppe PATTI, Marco MORELLI, Giuseppe BARILLARO
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Patent number: 10825954Abstract: A light-emitting device may include a semiconductor body having a first conductivity type, with a front side and a back side. The light-emitting device may also include a porous-silicon region which extends in the semiconductor body at the front side, and a cathode region in direct lateral contact with the porous-silicon region. The light-emitting device may further include a barrier region of electrically insulating material, which extends in direct contact with the cathode region at the bottom side of the cathode region so that, in use, an electric current flows in the semiconductor body through lateral portions of the cathode region.Type: GrantFiled: May 18, 2018Date of Patent: November 3, 2020Assignee: STMICROELECTRONICS S.R.L.Inventors: Marco Morelli, Fabrizio Fausto Renzo Toia, Giuseppe Barillaro, Marco Sambi
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Patent number: 10796942Abstract: A technique to make silicon oxide regions from porous silicon and related semiconductor structures are disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.Type: GrantFiled: August 20, 2018Date of Patent: October 6, 2020Assignee: STMICROELECTRONICS S.r.l.Inventors: Simone Dario Mariani, Fabrizio Fausto Renzo Toia, Marco Sambi, Davide Giuseppe Patti, Marco Morelli, Giuseppe Barillaro
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Publication number: 20200152377Abstract: An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding.Type: ApplicationFiled: January 16, 2020Publication date: May 14, 2020Applicant: STMicroelectroics S.r.l.Inventors: Vincenzo PALUMBO, Gabriella GHIDINI, Enzo CAROLLO, Fabrizio Fausto Renzo TOIA
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Publication number: 20200058540Abstract: A technique to make silicon oxide regions from porous silicon and related semiconductor structures are disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.Type: ApplicationFiled: August 20, 2018Publication date: February 20, 2020Inventors: Simone Dario MARIANI, Fabrizio Fausto Renzo TOIA, Marco SAMBI, Davide Giuseppe PATTI, Marco MORELLI, Giuseppe BARILLARO
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Patent number: 10541079Abstract: An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding.Type: GrantFiled: February 5, 2019Date of Patent: January 21, 2020Assignee: STMicroelectronics S.r.l.Inventors: Vincenzo Palumbo, Gabriella Ghidini, Enzo Carollo, Fabrizio Fausto Renzo Toia
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Patent number: 10535767Abstract: A process of forming integrated electronic device having a semiconductor body includes: forming a first electrode region having a first type of conductivity; forming a second electrode region having a second type of conductivity, which forms a junction with the first electrode region; and forming a nanostructured semiconductor region, which extends in one of the first and second electrode regions.Type: GrantFiled: January 31, 2019Date of Patent: January 14, 2020Assignee: STMICROELECTRONICS S.R.L.Inventors: Marco Sambi, Fabrizio Fausto Renzo Toia, Marco Marchesi, Marco Morelli, Riccardo Depetro, Giuseppe Barillaro, Lucanos Marsilio Strambini
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Publication number: 20190221652Abstract: A vertical-conduction semiconductor electronic device includes: a semiconductor body; a body region in the semiconductor body; a source terminal in the body region; a drain terminal spatially opposite to the source region; and a trench gate extending in depth in the semiconductor body through the body region and the source region. The trench gate includes a dielectric region of porous silicon oxide buried in the semiconductor body, and a gate conductive region extending between the dielectric region of porous silicon oxide and the first side.Type: ApplicationFiled: January 14, 2019Publication date: July 18, 2019Inventors: Davide Giuseppe PATTI, Marco SAMBI, Fabrizio Fausto Renzo TOIA, Simone Dario MARIANI, Elisabetta PIZZI, Giuseppe BARILLARO
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Publication number: 20190221678Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.Type: ApplicationFiled: January 14, 2019Publication date: July 18, 2019Applicant: STMicroelectronics S.r.l.Inventors: Flavio Francesco VILLA, Marco MORELLI, Marco MARCHESI, Simone Dario MARIANI, Fabrizio Fausto Renzo TOIA
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Publication number: 20190172631Abstract: An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding.Type: ApplicationFiled: February 5, 2019Publication date: June 6, 2019Applicant: STMicroelectronics S.r.l.Inventors: Vincenzo PALUMBO, Gabriella GHIDINI, Enzo CAROLLO, Fabrizio Fausto Renzo TOIA
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Publication number: 20190165170Abstract: A process of forming integrated electronic device having a semiconductor body includes: forming a first electrode region having a first type of conductivity; forming a second electrode region having a second type of conductivity, which forms a junction with the first electrode region; and forming a nanostructured semiconductor region, which extends in one of the first and second electrode regions.Type: ApplicationFiled: January 31, 2019Publication date: May 30, 2019Inventors: Marco SAMBI, Fabrizio Fausto Renzo TOIA, Marco MARCHESI, Marco MORELLI, Riccardo DEPETRO, Giuseppe BARILLARO, Lucanos Marsilio STRAMBINI
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Patent number: 10236115Abstract: An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding.Type: GrantFiled: June 8, 2015Date of Patent: March 19, 2019Assignee: STMicroelectronics S.r.l.Inventors: Vincenzo Palumbo, Gabriella Ghidini, Enzo Carollo, Fabrizio Fausto Renzo Toia
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Patent number: 10236378Abstract: An integrated electronic device having a semiconductor body including: a first electrode region having a first type of conductivity; and a second electrode region having a second type of conductivity, which forms a junction with the first electrode region. The integrated electronic device further includes a nanostructured semiconductor region, which extends in one of the first and second electrode regions.Type: GrantFiled: March 13, 2017Date of Patent: March 19, 2019Assignee: STMICROELECTRONICS S.R.L.Inventors: Marco Sambi, Fabrizio Fausto Renzo Toia, Marco Marchesi, Marco Morelli, Riccardo Depetro, Giuseppe Barillaro, Lucanos Marsilio Strambini
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Publication number: 20180269357Abstract: A light-emitting device may include a semiconductor body having a first conductivity type, with a front side and a back side. The light-emitting device may also include a porous-silicon region which extends in the semiconductor body at the front side, and a cathode region in direct lateral contact with the porous-silicon region. The light-emitting device may further include a barrier region of electrically insulating material, which extends in direct contact with the cathode region at the bottom side of the cathode region so that, in use, an electric current flows in the semiconductor body through lateral portions of the cathode region.Type: ApplicationFiled: May 18, 2018Publication date: September 20, 2018Inventors: Marco Morelli, Fabrizio Fausto Renzo Toia, Giuseppe Barillaro, Marco Sambi
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Patent number: 10062757Abstract: A semiconductor device includes: a semiconductor body including an active region that houses an electronic component and a passive dielectric region surrounding the active region; a conductive buried region, of metallic material or metallic alloy, which extends in the semiconductor body in the active region; and one or more electrical contacts, of metallic material, which extend between the conductive buried region and a top surface of the semiconductor body, and form respective paths for electrical access to the conductive buried region.Type: GrantFiled: August 29, 2016Date of Patent: August 28, 2018Assignee: STMICROELECTRONICS S.R.L.Inventors: Fabrizio Fausto Renzo Toia, Claudio Contiero, Elisabetta Pizzi, Simone Dario Mariani