Patents by Inventor Fabrizio Ghironi

Fabrizio Ghironi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6504253
    Abstract: An electric connection structure connecting a first silicon body to conductive regions provided on the surface of a second silicon body arranged on the first body. The electric connection structure includes at least one plug region of silicon, which extends through the second body; at least one insulation region laterally surrounding the plug region; and at least one conductive electromechanical connection region arranged between the first body and the second body, and in electrical contact with the plug region and with conductive regions of the first body. To form the plug region, trenches are dug in a first wafer and are filled, at least partially, with insulating material. The plug region is fixed to a metal region provided on a second wafer, by performing a low-temperature heat treatment which causes a chemical reaction between the metal and the silicon. The first wafer is thinned until the trenches and electrical connections are formed on the free face of the first wafer.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: January 7, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ubaldo Mastromatteo, Fabrizio Ghironi, Roberto Aina, Mauro Bombonati
  • Patent number: 6498053
    Abstract: An electric connection structure connecting a first silicon body to conductive regions provided on the surface of a second silicon body arranged on the first body. The electric connection structure includes at least one plug region of silicon, which extends through the second body; at least one insulation region laterally surrounding the plug region; and at least one conductive electromechanical connection region arranged between the first body and the second body, and in electrical contact with the plug region and with conductive regions of the first body. To form the plug region, trenches are dug in a first wafer and are filled, at least partially, with insulating material. The plug region is fixed to a metal region provided on a second wafer, by performing a low-temperature heat treatment which causes a chemical reaction between the metal and the silicon. The first wafer is thinned until the trenches and electrical connections are formed on the free face of the first wafer.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: December 24, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Ubaldo Mastromatteo, Fabrizio Ghironi, Roberto Aina, Mauro Bombonati
  • Publication number: 20020135062
    Abstract: An electric connection structure connecting a first silicon body to conductive regions provided on the surface of a second silicon body arranged on the first body. The electric connection structure includes at least one plug region of silicon, which extends through the second body; at least one insulation region laterally surrounding the plug region; and at least one conductive electromechanical connection region arranged between the first body and the second body, and in electrical contact with the plug region and with conductive regions of the first body. To form the plug region, trenches are dug in a first wafer and are filled, at least partially, with insulating material. The plug region is fixed to a metal region provided on a second wafer, by performing a low-temperature heat treatment which causes a chemical reaction between the metal and the silicon. The first wafer is thinned until the trenches and electrical connections are formed on the free face of the first wafer.
    Type: Application
    Filed: May 21, 2002
    Publication date: September 26, 2002
    Applicant: STMicroelectronics S.r.I.
    Inventors: Ubaldo Mastromatteo, Fabrizio Ghironi, Roberto Aina, Mauro Bombonati
  • Publication number: 20010038148
    Abstract: An electric connection structure connecting a first silicon body to conductive regions provided on the surface of a second silicon body arranged on the first body. The electric connection structure includes at least one plug region of silicon, which extends through the second body; at least one insulation region laterally surrounding the plug region; and at least one conductive electromechanical connection region arranged between the first body and the second body, and in electrical contact with the plug region and with conductive regions of the first body. To form the plug region, trenches are dug in a first wafer and are filled, at least partially, with insulating material. The plug region is fixed to a metal region provided on a second wafer, by performing a low-temperature heat treatment which causes a chemical reaction between the metal and the silicon. The first wafer is thinned until the trenches and electrical connections are formed on the free face of the first wafer.
    Type: Application
    Filed: April 27, 2001
    Publication date: November 8, 2001
    Inventors: Ubaldo Mastromatteo, Fabrizio Ghironi, Roberto Aina, Mauro Bombonati
  • Patent number: 5152168
    Abstract: A method for the quantitative assessment of the degree of geometrical deformation undergone by a surface profile of a wafer following the formation of a conformal surface layer employs a simple mechanical profilometer, whose stylus is run over a target morphological detail comprising at least two mutually parallel ridges or reliefs which rise above the plane of the surface of the wafer for a height of between 0.1 and 0.5 .mu.m, and which enclose between them a depression of a width of between 2 and 4 .mu.m, in order to determine the elevation of the bottom of the valley between the two ridges relative to the plane of the surface of the wafer from which the ridges rise following the formation of one or more similar surface layers. The vertical measurement of the elevation undergone by the bottom of the valley in itself represents a quantitative index of the vertical and horizontal geometrical deformation undergone by the details of the surface profile of the wafer.
    Type: Grant
    Filed: December 21, 1990
    Date of Patent: October 6, 1992
    Assignee: SGS-Thomson Microelectronics, s.r.l.
    Inventors: Gabriele Barlocchi, Fabrizio Ghironi