Abstract: A hinge includes a first fixing bracket, a shaft and a swivel bracket. The first fixing bracket includes two first support pieces and a first connection piece. The two first support pieces are arranged in parallel to each other, and the first connection piece is connected to the two second support pieces. The two first support pieces are respectively provided with a shaft hole and the shaft holes are arranged coaxially along a central axis. At least one of the first support pieces is provided with one limiting extension portion extending in a direction in parallel to the central axis at an upper front end of the first support piece and extending towards the other first support piece. The shaft is inserted into the shaft hole.

Abstract: A hinge includes a seat, a shaft, a swivel bracket and at least one limiting bar. The seat includes two support portions. An accommodation area is defined between the two support portions. The two support portions are respectively provided with a shaft hole. The two shaft holes are arranged coaxially and connected to the accommodation area. The shaft includes a coupling section and two pivoting sections. The coupling section is located between the two pivoting sections. The two pivoting sections are respectively provided in one of the two shaft holes in a rotatable manner, and the coupling section is in the accommodation area. The swivel bracket includes a mounting plate, a sleeve piece and at least one extension portion. The mounting plate includes an inner surface, an outer surface, and a bottom edge. The sleeve piece extends from the bottom edge of the mounting plate and is wound at a side corresponding to the inner surface.

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Abstract: A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.

Abstract: A switched capacitor converter includes plural switch units. The switch units are configured to switch a coupling relationship of a capacitor between a first power and a second power, wherein at least one of the switch units includes a switch circuit. The switch circuit includes a first switch, a second switch, and a switch driving circuit, wherein the conduction resistance of the first switch is greater than the conduction resistance of the second switch, and the parasitic capacitance of the first switch is less than the parasitic capacitance of the second switch. The switch driving circuit turns on the first switch before the second switch is turned on and/or turns off the first switch after the second switch is turned off, such that the switching loss of the switch circuit is less than a predetermined target value.

Abstract: A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Abstract: A switched capacitor converter includes plural switch units. The switch units are configured to switch a coupling relationship of a capacitor between a first power and a second power, wherein at least one of the switch units includes a switch circuit. The switch circuit includes a first switch, a second switch, and a switch driving circuit, wherein the conduction resistance of the first switch is greater than the conduction resistance of the second switch, and the parasitic capacitance of the first switch is less than the parasitic capacitance of the second switch. The switch driving circuit turns on the first switch before the second switch is turned on and/or turns off the first switch after the second switch is turned off, such that the switching loss of the switch circuit is less than a predetermined target value.

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

Abstract: A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Abstract: Pressure assisted positioning method and device thereof are disclosed in the present invention. The pressure assisted positioning device is exerted for positioning a target under the circumstance of altitude change since the target enters a specific region. The pressure assisted positioning method includes the following steps. First, confirming the entrance of the specific region of the target and detecting a plurality of pressure data. Then, calculating a pressure variation between the two selected pressure data. At last, comparing the pressure variation to a threshold. An altitude change within the specific region is confirmed as the pressure variation is greater than the threshold. On the other hand, as the pressure variation is greater than the threshold, it refers to no altitude change within the specific region.

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Abstract: A head-mounted display device includes a display portion, a main frame, two arms, and two adjusting pieces. The main frame carries the display portion. The arms are disposed on opposite sides of the main frame, and the end portions of the arms are pivotally connected to the main frame such that the arms are adapted to rotate away from the main frame during an unfolding process and adapted to rotate toward the main frame during a folding process. The adjusting pieces are respectively disposed on pivot paths of the arms, and the adjusting piece is adapted to from a structural interference with the corresponding arm and the main frame during the unfolding process to limit a degree of rotation of the arm.

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Abstract: A foldable display device has a flexible display panel, a support module, and at least one positioning module. The support module has a middle platform and a pair of side platforms. The positioning module has a pair of positioning gears respectively fixed to the intermediate platform on a pair of gear axes parallel to each other and a pair of planetary gears respectively fixed to the pair of side platforms on a pair of gear axes parallel to each other. The pair of planetary gears are respectively engaged with the pair of positioning gears to respectively move around the pair of positioning gears along a pair of motion paths, so that the pair of side platforms are switched between a flattened state and a folded state with respect to the intermediate platform to flatten or bend the flexible display panel.

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

Abstract: A head-mounted display device includes a display portion, a main frame, two arms, and two adjusting pieces. The main frame carries the display portion. The arms are disposed on opposite sides of the main frame, and the end portions of the arms are pivotally connected to the main frame such that the arms are adapted to rotate away from the main frame during an unfolding process and adapted to rotate toward the main frame during a folding process. The adjusting pieces are respectively disposed on pivot paths of the arms, and the adjusting piece is adapted to from a structural interference with the corresponding arm and the main frame during the unfolding process to limit a degree of rotation of the arm.