Patents by Inventor Fan-Ming Kuo
Fan-Ming Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220158878Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chaitanya Palusa, Rob Abbott, Rolando Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh, Fan-ming Kuo
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Patent number: 11240075Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.Type: GrantFiled: January 25, 2021Date of Patent: February 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chaitanya Palusa, Rob Abbott, Rolando Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh, Fan-ming Kuo
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Patent number: 11183262Abstract: A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data.Type: GrantFiled: April 17, 2020Date of Patent: November 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Ruei Li, Fan-Ming Kuo, Wei-Li Chen
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Publication number: 20210327528Abstract: A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data.Type: ApplicationFiled: April 17, 2020Publication date: October 21, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mao-Ruei Li, Fan-Ming Kuo, Wei-Li Chen
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Publication number: 20210218605Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.Type: ApplicationFiled: January 25, 2021Publication date: July 15, 2021Inventors: Chaitanya Palusa, Rob Abbott, Rolando Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh, Fan-ming Kuo
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Patent number: 10904044Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.Type: GrantFiled: January 13, 2020Date of Patent: January 26, 2021Inventors: Chaitanya Palusa, Rob Abbott, Rolando Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh, Fan-ming Kuo
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Publication number: 20200252248Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.Type: ApplicationFiled: January 13, 2020Publication date: August 6, 2020Inventors: Chaitanya Palusa, Rob Abbott, Rolando Ramirez, Wei-Li Chen, Dirk Pfaff, Cheng-Hsiang Hsieh, Fan-ming Kuo
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Patent number: 9991721Abstract: A transformer includes first and second semiconductor substrates. The first semiconductor substrate includes a first circuit, a first coil providing a first impedance, and a first capacitor coupled in parallel with the first coil. The second semiconductor substrate includes a second circuit, a second coil providing a second impedance and inductively coupled with the first coil, and a second capacitor coupled in parallel with the second coil.Type: GrantFiled: October 21, 2015Date of Patent: June 5, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jun-De Jin, Fan-Ming Kuo, Huan-Neng Chen, Ming-Hsien Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh
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Patent number: 9350324Abstract: The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed.Type: GrantFiled: December 27, 2012Date of Patent: May 24, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Hsiung Lee, Shi-Hung Wang, Kuang-Kai Yen, Wei-Li Chen, Yung-Hsu Chuang, Shih-Hung Lan, Fan-ming Kuo, Chewn-Pu Jou, Fu-Lung Hsueh
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Publication number: 20160043576Abstract: A transformer includes first and second semiconductor substrates. The first semiconductor substrate includes a first circuit, a first coil providing a first impedance, and a first capacitor coupled in parallel with the first coil. The second semiconductor substrate includes a second circuit, a second coil providing a second impedance and inductively coupled with the first coil, and a second capacitor coupled in parallel with the second coil.Type: ApplicationFiled: October 21, 2015Publication date: February 11, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jun-De JIN, Fan-Ming KUO, Huan-Neng CHEN, Ming-Hsien TSAI, Hsieh-Hung HSIEH, Tzu-Jin YEH
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Patent number: 9177715Abstract: A transformer includes first and second semiconductor substrates. The first semiconductor substrate includes a first circuit, a first coil providing a first impedance, and a first capacitor coupled in parallel with the first coil. The second semiconductor substrate includes a second circuit, a second coil providing a second impedance and inductively coupled with the first coil, and a second capacitor coupled in parallel with the second coil.Type: GrantFiled: November 23, 2010Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jun-De Jin, Fan-Ming Kuo, Huan-Neng Chen, Ming Hsien Tsai, Hsieh-Hung Hsieh, Tzu-Jin Yeh
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Patent number: 9098757Abstract: A semiconductor wafer includes a plurality of dies. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit and a coil. The RFID tag circuit includes a tag core, an RF front-end circuit, an ID decoder, a comparator and conductive line for a unique ID. The RF front-end circuit is configured to receive electromagnetic signals through the coil in each of the plurality of dies and to convert the received electromagnetic signals into commands. The ID decoder is configured to receive the commands and to generate an expect ID. The comparator is configured to compare the unique ID with the expect ID to generate a comparison result. The comparison result is arranged to decide if the tag core is configured to receive commands.Type: GrantFiled: June 25, 2013Date of Patent: August 4, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Hsiung Lee, Kuang-Kai Yen, Shi-Hung Wang, Yung-Hsu Chuang, Huan-Neng Chen, Wei-Li Chen, Shih-Hung Lan, Yi-Hsuan Liu, Fan-Ming Kuo, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
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Publication number: 20140184296Abstract: The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed.Type: ApplicationFiled: December 27, 2012Publication date: July 3, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Hsiung Lee, Shi-Hung Wang, Kuang-Kai Yen, Wei-Li Chen, Yung-Hsu Chuang, Shih-Hung Lan, Fan-Ming Kuo, Chewn-Pu Jou, Fu-Lung Hsueh
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Publication number: 20140145749Abstract: A semiconductor wafer includes a plurality of dies. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit and a coil. The RFID tag circuit includes a tag core, an RF front-end circuit, an ID decoder, a comparator and conductive line for a unique ID. The RF front-end circuit is configured to receive electromagnetic signals through the coil in each of the plurality of dies and to convert the received electromagnetic signals into commands. The ID decoder is configured to receive the commands and to generate an expect ID. The comparator is configured to compare the unique ID with the expect ID to generate a comparison result. The comparison result is arranged to decide if the tag core is configured to receive commands.Type: ApplicationFiled: June 25, 2013Publication date: May 29, 2014Inventors: Tsung-Hsiung Lee, Kuang-Kai Yen, Shi-Hung Wang, Yung-Hsu Chuang, Huan-Neng Chen, Wei-Li Chen, Shih-Hung Lan, Yi-Hsuan Liu, Fan-Ming Kuo, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
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Patent number: 8629694Abstract: A voltage scaling circuit includes a first critical path and an edge detection unit. The first critical path includes an input and an output. The edge detection unit includes a first input, a second input, a counter and a time-to-digital converter (TDC). The input of the first critical path is electrically connected to the first input of the edge detection unit, and the output of the critical path is electrically connected to the second input of the edge detection unit. The counter is configured to measure a duration between an active edge of a start signal on the first input of the edge detection unit and an active edge of a stop signal on the second input of the edge detection unit in a clock period basis. The TDC is configured to measure a beginning portion and an end portion of the duration.Type: GrantFiled: November 5, 2012Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shi-Hung Wang, Tsung-Hsiung Li, Kuang-Kai Yen, Wei-Li Chen, Chewn-Pu Jou, Fan-Ming Kuo
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Publication number: 20120126630Abstract: A transformer includes first and second semiconductor substrates. The first semiconductor substrate includes a first circuit, a first coil providing a first impedance, and a first capacitor coupled in parallel with the first coil. The second semiconductor substrate includes a second circuit, a second coil providing a second impedance and inductively coupled with the first coil, and a second capacitor coupled in parallel with the second coil.Type: ApplicationFiled: November 23, 2010Publication date: May 24, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jun-De JIN, Fan-Ming KUO, Huan-Neng CHEN, Ming Hsien TSAI, Hsieh-Hung HSIEH, Tzu-Jin YEH
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Patent number: 6834089Abstract: A tangent angle computation device and associated DQPSK decoder. The computation device uses an eight-bit divider and a four-quadrant technique for finding a quantized angular value from an incoming signal. The quantized angular value is subsequently used to decode the incoming signal.Type: GrantFiled: March 27, 2001Date of Patent: December 21, 2004Assignee: Macronix International Co., Ltd.Inventors: Terng-Yin Hsu, Chen-Yi Lee, Fan-Ming Kuo
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Publication number: 20040042567Abstract: A method of operating a matched filter of a point access memory (PAM) with variable lengths, suitable for a data storage region to store a received signal and for the matched filter to store a PN sequence in a storage region for reference values. The received signal comprises a plurality of sample data. The method of operating the matched filter of the PAM with variable lengths comprises: storing each sample data in the data storage region; shifting the PN sequence in the storage region for reference values to a corresponding position when all the sample data is stored in the data storage region; and performing a matching operation to match all the stored sample data and the PN sequence that are positioned in the corresponding position.Type: ApplicationFiled: March 27, 2001Publication date: March 4, 2004Inventors: Terng-Yin Hsu, Chen-Yi Lee, Fan-Ming Kuo
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Publication number: 20020122506Abstract: A tangent angle computation device and associated DQPSK decoder. The computation device uses an eight-bit divider and a four-quadrant technique for finding a quantized angular value from an incoming signal. The quantized angular value is subsequently used to decode the incoming signal.Type: ApplicationFiled: March 27, 2001Publication date: September 5, 2002Inventors: Terng-Yin Hsu, Chen-Yi Lee, Fan-Ming Kuo
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Patent number: 5442660Abstract: Frequency hopping enables a plurality of channels to share the same bandwidth without interference. The present invention utilizes Galois Field theory to define frequency hopping sequences for a plurality of channels which share the same bandwidth.Type: GrantFiled: January 10, 1994Date of Patent: August 15, 1995Assignee: Industrial Technology Research InstituteInventors: Fan-Ming Kuo, Kwang-Cheng Chen