Patents by Inventor Fan Wan Lai
Fan Wan Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9041203Abstract: A system and method for manufacturing a semiconductor device including multi-layer bitlines. The location of the bitlines in multiple layers provides for increased spacing and increased width thereby overcoming the limitations of the pitch dictated by the semiconductor fabrication process used. The bitlines locations in multiple layers thus allows the customization of the spacing and width according to the use of a semiconductor device.Type: GrantFiled: October 10, 2008Date of Patent: May 26, 2015Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Zubin Patel, Nian Yang, Fan Wan Lai, Alok Nandini Roy
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Patent number: 8560756Abstract: A hybrid memory system is provided that combines the advantages of NAND flash memory devices with the advantages of NOR flashes memory devices. The system includes a NAND flash memory portion to provide mass storage and fast programming/erasure capabilities of conventional NAND flash memory devices. The system further comprises a NOR flash memory portion to provide code storage and fast random reading capabilities of conventional NOR flash memory devices. Accordingly, the hybrid memory system provides both mass storage and code storage along with fast programming/erasure speeds and fast random access speeds.Type: GrantFiled: October 17, 2007Date of Patent: October 15, 2013Assignee: Spansion LLCInventors: Nian Yang, Jiang Li, Fan Wan Lai
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Patent number: 7804715Abstract: A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved.Type: GrantFiled: May 5, 2008Date of Patent: September 28, 2010Assignee: Spansion LLCInventors: Hongtau Mu, Nian Yang, Fan Wan Lai, Guowei Wang
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Publication number: 20100090337Abstract: A system and method for manufacturing a semiconductor device including multi-layer bitlines. The location of the bitlines in multiple layers provides for increased spacing and increased width thereby overcoming the limitations of the pitch dictated by the semiconductor fabrication process used. The bitlines locations in multiple layers thus allows the customization of the spacing and width according to the use of a semiconductor device.Type: ApplicationFiled: October 10, 2008Publication date: April 15, 2010Inventors: Zubin PATEL, Nian YANG, Fan Wan LAI, Alok Nandini ROY
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Publication number: 20090273998Abstract: A memory device includes a sense amplifier to sense the state of a bitcell. The sense amplifier includes two input terminals connected via a switch. One of the input terminals is connected to a node, whereby a current through the node represents a difference in current drawn by a bitcell and a reference current. During a first phase, the switch between the input terminals of the sense amplifier is closed, so that a common voltage is applied to both input terminals. During a second phase, the switch is opened, and the sense amplifier senses a state of information stored at the bitcell based on the current through the node. By using the switch to connect and disconnect the inputs of the sense amplifier in the two phases, the accuracy and speed with which the state of the information stored at the bitcell can be determined is improved.Type: ApplicationFiled: May 5, 2008Publication date: November 5, 2009Applicant: SPANSION LLCInventors: Hongtau Mu, Nian Yang, Fan Wan Lai, Guowei Wang
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Patent number: 7613044Abstract: A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).Type: GrantFiled: December 5, 2007Date of Patent: November 3, 2009Assignee: Spansion LLCInventors: Nian Yang, Boon-Aik Ang, Yonggang Wu, Guowei Wang, Fan Wan Lai
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Patent number: 7532518Abstract: Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their location, which can in turn cause non-uniformity in the speed of high voltage operations on the memory array such as programming. The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell.Type: GrantFiled: June 25, 2007Date of Patent: May 12, 2009Assignee: Spansion LLCInventors: Nian Yang, Fan Wan Lai, Aaron Lee
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Publication number: 20090106481Abstract: A hybrid memory system is provided that combines the advantages of NAND flash memory devices with the advantages of NOR flashes memory devices. The system includes a NAND flash memory portion to provide mass storage and fast programming/erasure capabilities of conventional NAND flash memory devices. The system further comprises a NOR flash memory portion to provide code storage and fast random reading capabilities of conventional NOR flash memory devices. Accordingly, the hybrid memory system provides both mass storage and code storage. along with fast programming/erasure speeds and fast random access speeds.Type: ApplicationFiled: October 17, 2007Publication date: April 23, 2009Applicant: SPANSION LLCInventors: Nian Yang, Jiang Li, Fan Wan Lai
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Publication number: 20080316830Abstract: Systems and methodologies are provided herein for increasing operation speed uniformity in a flash memory device. Due to the characteristics of a typical flash memory array, memory cells in a memory array may experience distributed substrate resistance that increases as the distance of the memory cell from an edge of the memory array increases. This difference in distributed substrate resistance can vary voltages supplied to different memory cells in the memory array depending on their location, which can in turn cause non-uniformity in the speed of high voltage operations on the memory array such as programming. The systems and methodologies provided herein reduce this non-uniformity in operation speed by providing compensated voltage levels to memory cells in a memory array based at least in part on the location of each respective memory cell.Type: ApplicationFiled: June 25, 2007Publication date: December 25, 2008Applicant: SPANSION LLCInventors: Nian Yang, Fan Wan Lai, Aaron Lee
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Publication number: 20080130371Abstract: A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).Type: ApplicationFiled: December 5, 2007Publication date: June 5, 2008Inventors: Nian Yang, Boon-Aik Ang, Yonggang Wu, Guowei Wang, Fan Wan Lai
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Patent number: 7345916Abstract: A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).Type: GrantFiled: June 12, 2006Date of Patent: March 18, 2008Assignee: Spansion LLCInventors: Nian Yang, Boon-Aik Ang, Yonggang Wu, Guowei Wang, Fan Wan Lai
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Publication number: 20070291550Abstract: A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).Type: ApplicationFiled: June 12, 2006Publication date: December 20, 2007Inventors: Nian Yang, Boon-Aik Ang, Yonggang Wu, Guowei Wang, Fan Wan Lai