Patents by Inventor Fan Yeung
Fan Yeung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8779598Abstract: Embodiments described herein provide a method of manufacturing integrated circuit (IC) devices. The method includes coupling a first surface of a first intermediate substrate to a first surface of a second intermediate substrate, forming a first plurality of patterned metal layers on a second surface of the first intermediate substrate to form a first substrate and a second plurality of patterned metal layers on a second surface of the second intermediate substrate to form a second substrate, and separating the first and second substrates. Each of the first substrate and the second substrate is configured to facilitate electrical interconnection between a respective IC die and a respective printed circuit board (PCB).Type: GrantFiled: June 28, 2011Date of Patent: July 15, 2014Assignee: Broadcom CorporationInventors: Fan Yeung, Raymond (Kwok Cheung) Tsang, Edward Law
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Patent number: 8378471Abstract: Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.Type: GrantFiled: January 22, 2010Date of Patent: February 19, 2013Assignee: ATI Technologies ULCInventors: Roden R. Topacio, Vincent Chan, Fan Yeung
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Publication number: 20130001791Abstract: Embodiments described herein provide a method of manufacturing integrated circuit (IC) devices. The method includes coupling a first surface of a first intermediate substrate to a first surface of a second intermediate substrate, forming a first plurality of patterned metal layers on a second surface of the first intermediate substrate to form a first substrate and a second plurality of patterned metal layers on a second surface of the second intermediate substrate to form a second substrate, and separating the first and second substrates. Each of the first substrate and the second substrate is configured to facilitate electrical interconnection between a respective IC die and a respective printed circuit board (PCB).Type: ApplicationFiled: June 28, 2011Publication date: January 3, 2013Applicant: Broadcom CorporationInventors: Fan YEUNG, Raymond (Kwok Cheung) TSANG, Edward LAW
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Patent number: 8226796Abstract: A collet is provided for picking up a die mounted on an adhesive surface. A flat platform at an end of the collet is configured to hold a planar surface of the die during pick-up of the die and a flange protruding from one side of the platform is operative to push against a side of the die which is substantially perpendicular to the planar surface of the die during a die pick-up process.Type: GrantFiled: January 14, 2009Date of Patent: July 24, 2012Assignee: ASM Assembly Automation LtdInventors: Yau Sun Fan, Wai Shing Ho, Hiu Leung Tse, Yee Fan Yeung, Ka On Yue
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Publication number: 20100175828Abstract: A collet is provided for picking up a die mounted on an adhesive surface. A flat platform at an end of the collet is configured to hold a planar surface of the die during pick-up of the die and a flange protruding from one side of the platform is operative to push against a side of the die which is substantially perpendicular to the planar surface of the die during a die pick-up process.Type: ApplicationFiled: January 14, 2009Publication date: July 15, 2010Inventors: Yau Sun Fan, Wai Shing Ho, Hiu Leung Tse, Yee Fan Yeung, Ka On Yue
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Publication number: 20100140798Abstract: Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.Type: ApplicationFiled: January 22, 2010Publication date: June 10, 2010Inventors: Roden R. Topacio, Vincent Chan, Fan Yeung
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Patent number: 7670939Abstract: Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.Type: GrantFiled: May 12, 2008Date of Patent: March 2, 2010Assignee: ATI Technologies ULCInventors: Roden R. Topacio, Vincent Chan, Fan Yeung
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Patent number: 7646083Abstract: Methods, systems, and apparatuses for integrated circuit packages and lead frames are provided. A quad flat no-lead (QFN) package includes a plurality of peripherally positioned pins, a die-attach paddle, an integrated circuit die, and an encapsulating material. The die-attach paddle is positioned within a periphery formed by the pins. The die is attached to the die-attach paddle. The encapsulating material encapsulates the die on the die-attach paddle, encapsulates bond wires connected between the die and the pins, and fills a space between the pins and the die-attach paddle. One or more of the pins are extended. An extended pin may be elongated, L shaped, T shaped, or “wishbone” shaped. The extended pin(s) enable wire bonding of additional ground, power, and I/O (input/output) pads of the die in a manner that does not significantly increase QFN package cost.Type: GrantFiled: March 31, 2008Date of Patent: January 12, 2010Assignee: Broadcom CorporationInventors: Fan Yeung, Sam Ziqun Zhao, Nir Matalon, Victor Fong
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Publication number: 20090278264Abstract: Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.Type: ApplicationFiled: May 12, 2008Publication date: November 12, 2009Inventors: Roden R. Topacio, Vincent Chan, Fan Yeung
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Publication number: 20090243054Abstract: Methods, systems, and apparatuses for integrated circuit packages and lead frames are provided. A quad flat no-lead (QFN) package includes a plurality of peripherally positioned pins, a die-attach paddle, an integrated circuit die, and an encapsulating material. The die-attach paddle is positioned within a periphery formed by the pins. The die is attached to the die-attach paddle. The encapsulating material encapsulates the die on the die-attach paddle, encapsulates bond wires connected between the die and the pins, and fills a space between the pins and the die-attach paddle. One or more of the pins are extended. An extended pin may be elongated, L shaped, T shaped, or “wishbone” shaped. The extended pin(s) enable wire bonding of additional ground, power, and I/O (input/output) pads of the die in a manner that does not significantly increase QFN package cost.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: BROADCOM CORPORATIONInventors: Fan Yeung, Sam Ziqun Zhao, Nir Matalon, Victor Fong
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Publication number: 20040038232Abstract: The present invention relates to promoters, enhancers and other regulatory elements that direct expression within tumor cells, comprising nucleotide sequences from the 5′ regulatory region, and transcriptionally active fragments thereof, that control expression of a renal cell carcinoma related protein, MN-CA9. Specifically provided are expression vectors, host cells and transgenic animals wherein an MN-CA9 regulatory region is capable of controlling expression of a heterologous gene, over-expressing an endogenous gene or an inhibitor of a pathological process or knocking out expression of a specific gene believed to be important in cancer development and/or progression. The invention also relates to methods for using said vectors, cells and animals for screening candidate molecules for agonists and antagonists of cancer development and/or progression.Type: ApplicationFiled: March 31, 2003Publication date: February 26, 2004Inventors: Thomas A Gardner, Chinghai Kao, Song-Chu Ko, Fan Yeung, Lelend W K Chung
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Publication number: 20030078224Abstract: The present invention provides methods and compositions for the delivery and expression of therapeutic genes for treating prostate and non-prostate tumors in a gene therapy setting with therapeutic genes driven by a super PSA promoter. This approach enhances the capability of increasing the size of therapeutic gene inserts and maintaining specificity and efficiency of genes expression. This form of gene therapy strategy can be applied either alone or in combination with other adjuvant therapies or used in combination with various gene therapy strategies to achieve the maximum effect in cancer treatment, and in normal and benign tissues to enhance therapeutic gains.Type: ApplicationFiled: April 24, 2002Publication date: April 24, 2003Inventors: Leland W.K. Chung, Fan Yeung, Chinghai Kao