Patents by Inventor Fan-Yu MIN

Fan-Yu MIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11244909
    Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The first electronic device is disposed on the wiring structure. The second electronic device is disposed on the wiring structure. The first electronic device and the second electronic device are disposed side by side. A gap between the first electronic device and the second electronic device is greater than or equal to about 150 ?m.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: February 8, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Fan-Yu Min, Chen-Hung Lee, Wei-Hang Tai, Yuan-Tzuo Luo, Wen-Yuan Chuang, Chun-Cheng Kuo, Chin-Li Kao
  • Publication number: 20210287999
    Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The first electronic device is disposed on the wiring structure. The second electronic device is disposed on the wiring structure. The first electronic device and the second electronic device are disposed side by side. A gap between the first electronic device and the second electronic device is greater than or equal to about 150 ?m.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 16, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Fan-Yu MIN, Chen-Hung LEE, Wei-Hang TAI, Yuan-Tzuo LUO, Wen-Yuan CHUANG, Chun-Cheng KUO, Chin-Li KAO
  • Patent number: 11107791
    Abstract: A semiconductor package structure includes a conductive structure, a first semiconductor chip, a second semiconductor chip, a first encapsulant and an upper semiconductor chip. The first semiconductor chip is electrically connected to the conductive structure. The first semiconductor chip includes at least one first conductive element disposed adjacent to a second surface thereof. The second semiconductor chip is electrically connected to the conductive structure and disposed next to the first semiconductor chip. The second semiconductor chip includes at least one second conductive element disposed adjacent to a second surface thereof. The first encapsulant is disposed on the conductive structure to cover the first semiconductor chip and the second semiconductor chip. The first conductive element and the second conductive element are exposed from the first encapsulant.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: August 31, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Fan-Yu Min, Chao-Hung Weng, Wei-Hang Tai, Chen-Hung Lee, Yu-Yuan Yeh
  • Patent number: 11094649
    Abstract: Present disclosure provides a semiconductor package structure, which includes a redistribution layer (RDL) structure, an electronic device, a first reinforcement structure, a second reinforcement structure, and an encapsulant. The RDL structure has a passivation layer and a patterned conductive layer disposed in the passivation layer. The electronic device is disposed on the RDL structure. The first reinforcement structure is disposed on the RDL structure and has a first modulus. The second reinforcement structure is disposed on the first reinforcement structure and has a second modulus substantially less than the first modulus. The encapsulant is disposed on the RDL structure and encapsulates the electronic device, the first reinforcement structure and the second reinforcement structure.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: August 17, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Fan-Yu Min, Chen-Hung Lee, Hsiu-Chi Liu, Liang-Chun Chen
  • Publication number: 20210225781
    Abstract: Present disclosure provides a semiconductor package structure, which includes a redistribution layer (RDL) structure, an electronic device, a first reinforcement structure, a second reinforcement structure, and an encapsulant. The RDL structure has a passivation layer and a patterned conductive layer disposed in the passivation layer. The electronic device is disposed on the RDL structure. The first reinforcement structure is disposed on the RDL structure and has a first modulus. The second reinforcement structure is disposed on the first reinforcement structure and has a second modulus substantially less than the first modulus. The encapsulant is disposed on the RDL structure and encapsulates the electronic device, the first reinforcement structure and the second reinforcement structure.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Fan-Yu MIN, Chen-Hung LEE, Hsiu-Chi LIU, Liang-Chun CHEN
  • Patent number: 10943800
    Abstract: An apparatus for packaging a semiconductor device is provided. The apparatus includes a first mold, a second mold and a support element. The first mold includes a plate. The second mold includes a carrier disposed corresponding to the plate. The carrier defines a hole penetrating the carrier. The support element is engaged with the hole for supporting an object to be molded.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 9, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Fan-Yu Min, Chao-Hung Weng, Liang-Chun Chen
  • Publication number: 20200294964
    Abstract: A semiconductor package structure includes a conductive structure, a first semiconductor chip, a second semiconductor chip, a first encapsulant and an upper semiconductor chip. The first semiconductor chip is electrically connected to the conductive structure. The first semiconductor chip includes at least one first conductive element disposed adjacent to a second surface thereof. The second semiconductor chip is electrically connected to the conductive structure and disposed next to the first semiconductor chip. The second semiconductor chip includes at least one second conductive element disposed adjacent to a second surface thereof. The first encapsulant is disposed on the conductive structure to cover the first semiconductor chip and the second semiconductor chip. The first conductive element and the second conductive element are exposed from the first encapsulant.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Fan-Yu MIN, Chao-Hung WENG, Wei-Hang TAI, Chen-Hung LEE, Yu-Yuan YEH
  • Publication number: 20180301361
    Abstract: An apparatus for packaging a semiconductor device is provided. The apparatus includes a first mold, a second mold and a support element. The first mold includes a plate. The second mold includes a carrier disposed corresponding to the plate. The carrier defines a hole penetrating the carrier. The support element is engaged with the hole for supporting an object to be molded.
    Type: Application
    Filed: April 18, 2017
    Publication date: October 18, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Fan-Yu MIN, Chao-Hung WENG, Liang-Chun CHEN