Abstract: Techniques for calibrating both temperature sensor circuitry and voltage sensor circuitry of temperature/voltage sensor circuitry by trimming variation in a bandgap reference voltage, which is common between the temperature sensor circuitry and the voltage sensor circuitry, to zero or approximately zero using a single trim value.

Abstract: Systems, methods, and circuitries are provided to control a gain setting in an analog-to-digital converter (ADC) that converts an analog signal to a digital signal based on a reference voltage. Temperature compensation circuitry includes a temperature gain correction circuitry and a combination circuitry. The temperature gain correction circuitry is configured to determine a correction term based on a temperature that affects the reference voltage. The combination circuitry is configured to combine the correction term with a calibration gain value to generate a corrected calibration gain value and provide the corrected calibration gain value to the ADC to control the gain setting.

Abstract: Techniques for calibrating both temperature sensor circuitry and voltage sensor circuitry of temperature/voltage sensor circuitry by trimming variation in a bandgap reference voltage, which is common between the temperature sensor circuitry and the voltage sensor circuitry, to zero or approximately zero using a single trim value.

Abstract: Representative implementations of devices and techniques provide correction for temperature sensor measurement error. In an example, the temperature sensor includes an analog-to-digital converter (ADC). The ADC output is error corrected using an iterative digital post-processing technique.

Abstract: Representative implementations of devices and techniques provide calibration for a chip-based temperature sensor. Two or more measurements are taken using a high resolution temperature sensor digitizer, and used to determine a calibration for the temperature sensor, based on a reference temperature value calculated from the measurements.

Abstract: Representative implementations of devices and techniques provide correction for temperature sensor measurement error. In an example, the temperature sensor includes an analog-to-digital converter (ADC). The ADC output is error corrected using an iterative digital post-processing technique.

Abstract: Embodiments relate to fault detection comparator circuitry and methods that can operate in conjunction with a power-on-reset (POR) scheme to put a chip into a reliable power-down mode upon fault detection to avoid disrupting the communication bus link such that other connected chips and the host can continue to operate. Power-on of the affected chip can then be carried out when the connection with that chip is restored.

Abstract: Representative implementations of devices and techniques provide calibration for a chip-based temperature sensor. Two or more measurements are taken using a high resolution temperature sensor digitizer, and used to determine a calibration for the temperature sensor, based on a reference temperature value calculated from the measurements.

Abstract: Embodiments relate to fault detection comparator circuitry and methods that can operate in conjunction with a power-on-reset (POR) scheme to put a chip into a reliable power-down mode upon fault detection to avoid disrupting the communication bus link such that other connected chips and the host can continue to operate. Power-on of the affected chip can then be carried out when the connection with that chip is restored.

Abstract: Embodiments relate to fault detection comparator circuitry and methods that can operate in conjunction with a power-on-reset (POR) scheme to put a chip into a reliable power-down mode upon fault detection to avoid disrupting the communication bus link such that other connected chips and the host can continue to operate. Power-on of the affected chip can then be carried out when the connection with that chip is restored.

Abstract: In accordance with an embodiment, a level shifter circuit includes a reconfigurable level shifting core coupled to a first node and a second node. The reconfigurable level shifting core is configured as a current mirror in a first mode, and as a cross-coupled device in a second mode. In the first mode, the current mirror mirrors a current at the first node to the second node, and in the second mode, the cross-coupled device produces a current at the second node in response to a voltage at the first node, and a current at the first node in response to a voltage at the second node.

Abstract: In accordance with an embodiment, a level shifter circuit includes a reconfigurable level shifting core coupled to a first node and a second node. The reconfigurable level shifting core is configured as a current mirror in a first mode, and as a cross-coupled device in a second mode. In the first mode, the current mirror mirrors a current at the first node to the second node, and in the second mode, the cross-coupled device produces a current at the second node in response to a voltage at the first node, and a current at the first node in response to a voltage at the second node.

Abstract: Embodiments relate to fault detection comparator circuitry and methods that can operate in conjunction with a power-on-reset (POR) scheme to put a chip into a reliable power-down mode upon fault detection to avoid disrupting the communication bus link such that other connected chips and the host can continue to operate. Power-on of the affected chip can then be carried out when the connection with that chip is restored.

Abstract: This disclosure relates to noise suppression in data transfers in transceivers of wireless devices.

Abstract: A semiconductor chip including an embedded comparator is provided with an on-chip test circuit for the comparator. The test circuit includes an analog input unit which, during a test mode of the chip, produces a range of analog voltage signals that are applied to a first input of the comparator and a threshold voltage signal that is applied to a second input of the comparator. A switch control unit is provided to control the application of a predetermined sequential pattern of these analog voltage signals to the first input of the comparator in synchrony with a clock signal supplied to the switch control unit during a predetermined test period. A digital measurement unit is provided to receive output signals from the comparator during the test period in response to the input patterns, to compare the output signals with the clock signal, and to measure and to store data relating thereto.

Abstract: In order to solve the problem of determining a barrier layer temperature in a semiconductor communication component (1) and thus to guarantee normal operation of the same, for example in a communication system (10) in the form of an xDSL connection card, according to the present invention temperature sensing means (20) for gauging the barrier layer temperature of a circuit arrangement on the communication semiconductor component (1) are integrated in the same. In accordance with the invention the communication system (10) comprises at least one communication semiconductor component (1) according to the invention and a control unit (12), that utilizes the values of the barrier layer temperature made available by the temperature sensing means, which are integrated in the communication semiconductor component (1), and this can be used for regulating cooling devices (18, 19) or for switching the communication semiconductor component (1) to an energy saving mode for example.

Abstract: This disclosure relates to noise suppression in data transfers in transceivers of wireless devices.

Abstract: A system includes a bandgap reference voltage circuit, a plurality of trimming resistors, a plurality of trimming switches to connect the bandgap reference voltage circuit to one or more of the plurality of trimming resistors, and an output terminal to connect to at least one of the bandgap reference voltage circuit and the plurality of trimming resistors. The system may provide a trimmed reference voltage independent of at least one of the resistance of any of the plurality of trimming switches and the voltage across any of the plurality of trimming switches.

Abstract: A semiconductor chip including an embedded comparator is provided with an on-chip test circuit for the comparator. The test circuit includes an analog input unit which, during a test mode of the chip, produces a range of analog voltage signals that are applied to a first input of the comparator and a threshold voltage signal that is applied to a second input of the comparator. A switch control unit is provided to control the application of a predetermined sequential pattern of these analog voltage signals to the first input of the comparator in synchrony with a clock signal supplied to the switch control unit during a predetermined test period. A digital measurement unit is provided to receive output signals from the comparator during the test period in response to the input patterns, to compare the output signals with the clock signal, and to measure and to store data relating thereto.

Abstract: An apparatus includes a transmitter, receiver or transceiver to couple to a communication link. An input receives one or more signals for a desired power level of the transmitter, receiver or transceiver. A power supply provides power to the transmitter, receiver or transceiver depending on at least the one or more signals.