Abstract: The present invention had disclosed an embedded processor based 3D acoustic imaging real-time signal processing device of modularized design; the system comprises an embedded GPU signal processing subsystem, a signal interaction subsystem and a signal acquisition subsystem. The system takes Tegra K1 embedded GPU processor as the core; Tegra K1 embedded GPU processor is provided with features of OpenGL4.4, OpenGL ES 3.1 and CUDA, which has high parallel image processing capability and abundant high-speed data interconnection interface; it is especially applicable to high-speed data transmission and effective calculation of image algorithm for 3D acoustic imaging real-time signal processing device. Meanwhile, it can realize high-speed data interaction between signal processing subsystem and numerous signal acquisition subsystems; the whole system has powerful data interaction capability and real-time parallel processing capability.

Abstract: The present discloses provides a decoding method, decoding apparatus and decoder for correcting burst errors. In particular, the decoding method for correcting burst errors comprises: computing an initial syndrome of a received data frame, wherein the data frame is encoded according to cyclic codes for correcting burst errors; determining error correctability of burst error contained in the data frame based on the computed initial syndrome; and processing the burst error in the data frame and outputting the processed data frame based on the determined error correctability. With the decoding method, decoding apparatus, and decoder of the present invention, error correctability of burst errors contained in a data frame can be determined before the data is send out, while having smaller decoding latency through determining the error correctability and error pattern of the burst errors contained in the data frame using initial syndrome of the data frame.

Abstract: Embodiments of the present invention provide a photographing processing method, a device and a computer storage medium. The method includes: receiving at least one instruction for selecting at least one object to be removed in a live view image according to a preset order; acquiring a live view image with selected object to be removed; and removing the at least one object to be removed in the live view image with selected object to be removed sequentially according to the preset order to obtain a photograph.

Abstract: Provided herein are methods, compositions, devices, and systems for the 3D printing of biomedical implants. In particular, methods and systems are provided for 3D printing of biomedical devices (e.g., endovascular stents) using photo-curable biomaterial inks (e.g., or methacrylated poly(diol citrate)).

Abstract: The present disclosure discloses a preparation method of pressed Scandia-doped dispenser cathode using microwave sintering. Embodiments of the present disclosure include dissolving some nitrates and ammonium metatungstate with deionized water to prepare a homogeneous solution. Precursor powder with uniform size is obtained by spray drying, the precursor powder is decomposed, and two-step reduction may be proceeded to form doped tungsten powder with uniform element distribution. The cathode is prepared by one-time microwave sintering. One-time forming of cathode sintering is realized, and sintering shrinkage and sintering time are reduced significantly. The method has excellent repeatability, and the cathode has a homogeneous structure and excellent emission performance at 950° C.

Abstract: The present discloses provides a decoding method, decoding apparatus and decoder for correcting burst errors. In particular, the decoding method for correcting burst errors comprises: computing an initial syndrome of a received data frame, wherein the data frame is encoded according to cyclic codes for correcting burst errors; determining error correctability of burst error contained in the data frame based on the computed initial syndrome; and processing the burst error in the data frame and outputting the processed data frame based on the determined error correctability. With the decoding method, decoding apparatus, and decoder of the present invention, error correctability of burst errors contained in a data frame can be determined before the data is send out, while having smaller decoding latency through determining the error correctability and error pattern of the burst errors contained in the data frame using initial syndrome of the data frame.

Abstract: A method of manufacturing carburized Lu2O3 doped Mo cathodes for thermionic emission for magnetrons is described. The Lu2O3 doped Mo powder is prepared by sol-gel method. The powder is reduced thoroughly in hydrogen atmosphere. Afterwards, the powder is die-pressed into pellets, followed by sintering in hydrogen and carburization in activated carbon powder to obtain the carburized Lu2O3 doped Mo cathode.

Abstract: The present discloses provides a decoding method, decoding apparatus and decoder for correcting burst errors. In particular, the decoding method for correcting burst errors comprises: computing an initial syndrome of a received data frame, wherein the data frame is encoded according to cyclic codes for correcting burst errors; determining error correctability of burst error contained in the data frame based on the computed initial syndrome; and processing the burst error in the data frame and outputting the processed data frame based on the determined error correctability. With the decoding method, decoding apparatus, and decoder of the present invention, error correctability of burst errors contained in a data frame can be determined before the data is send out, while having smaller decoding latency through determining the error correctability and error pattern of the burst errors contained in the data frame using initial syndrome of the data frame.

Abstract: Embodiments of the present invention provide a photographing processing method, a device and a computer storage medium. The method includes: receiving at least one instruction for selecting at least one object to be removed in a live view image according to a preset order; acquiring a live view image with selected object to be removed; and removing the at least one object to be removed in the live view image with selected object to be removed sequentially according to the preset order to obtain a photograph.

Abstract: The present discloses provides a decoding method, decoding apparatus and decoder for correcting burst errors. In particular, the decoding method for correcting burst errors comprises: computing an initial syndrome of a received data frame, wherein the data frame is encoded according to cyclic codes for correcting burst errors; determining error correctability of burst error contained in the data frame based on the computed initial syndrome; and processing the burst error in the data frame and outputting the processed data frame based on the determined error correctability. With the decoding method, decoding apparatus, and decoder of the present invention, error correctability of burst errors contained in a data frame can be determined before the data is send out, while having smaller decoding latency through determining the error correctability and error pattern of the burst errors contained in the data frame using initial syndrome of the data frame.

Abstract: This invention discloses a FPGA based high-speed low-latency floating-point accumulation and its implementation method. Floating accumulation of this invention comprises a floating-point adder unit, numerous intermediate result buffers, an input control unit and an output control unit. The floating-point accumulation implementation method of this invention is used for gradation of the whole accumulation calculation process to ensure cross execution of accumulation calculation processes and graded storage of intermediate results of accumulation calculation at different levels; meanwhile, the operation in the mode of pure flow line can significantly improve utilization rate of internal floating-point adder, and maintain relatively low latency to output of final results of floating-point accumulation calculation.

Abstract: The present invention discloses a multi-core processor based high-speed digital textile printing processing system, comprising a gigabit Ethernet interface, a I2C interface, a Stream IO interface and a multi-core processor; the multi-core processor comprises a command receiving unit, a command processing unit, a command output unit, a data receiving unit, a compressed data buffer unit, a data decompression unit, a decompressed data buffer unit and a data output unit; meanwhile, the present invention also disclosed a multi-core processor based high-speed digital textile printing processing method. The present invention is centered on high-performance multi-core processor, which aims to implement high-speed transmission of printing data from PC to printing nozzle via the gigabit Ethernet and Stream IO interface as well as processing and transfer of printing commands via the gigabit Ethernet and I2C interface.

Abstract: A method, apparatus and decoder for decoding cyclic code are proposed. The decoding method comprises: receiving a transmitted cyclic code; calculating the initial syndrome of the cyclic code; by using the initial syndrome and w prestored successive shift operators, calculating respectively w successive shift syndromes in a w-bit window of the cyclic code in parallel; and detecting/locating error in the cyclic code based on the obtained syndromes. The decoding apparatus corresponds to the above method. And the corresponding decoder is also proposed in this invention. The method, apparatus and decoder according to the invention could process the cyclic code within a window width and thus enhance decoding efficiency in parallel.

Abstract: The present invention discloses a multi-core processor based high-speed digital textile printing processing system, comprising a gigabit Ethernet interface, a I2C interface, a Stream IO interface and a multi-core processor; the multi-core processor comprises a command receiving unit, a command processing unit, a command output unit, a data receiving unit, a compressed data buffer unit, a data decompression unit, a decompressed data buffer unit and a data output unit; meanwhile, the present invention also disclosed a multi-core processor based high-speed digital textile printing processing method. The present invention is centered on high-performance multi-core processor, which aims to implement high-speed transmission of printing data from PC to printing nozzle via the gigabit Ethernet and Stream IO interface as well as processing and transfer of printing commands via the gigabit Ethernet and I2C interface.

Abstract: The present discloses provides a decoding method, decoding apparatus and decoder for correcting burst errors. In particular, the decoding method for correcting burst errors comprises: computing an initial syndrome of a received data frame, wherein the data frame is encoded according to cyclic codes for correcting burst errors; determining error correctability of burst error contained in the data frame based on the computed initial syndrome; and processing the burst error in the data frame and outputting the processed data frame based on the determined error correctability. With the decoding method, decoding apparatus, and decoder of the present invention, error correctability of burst errors contained in a data frame can be determined before the data is send out, while having smaller decoding latency through determining the error correctability and error pattern of the burst errors contained in the data frame using initial syndrome of the data frame.

Abstract: The present invention relates to methods and applications of using Drosophila cells to produce virus-like particles. Virus-like particles of enveloped viruses produced by the methods of the present invention have proteins correctly expressed, cleaved, and assembled. Ultimately, virus-like particles having good immunogenicity are obtained. The present invention also provides recombinant cells expressing virus-like particles and compositions containing virus-like particles.

Abstract: This invention discloses a FPGA based high-speed low-latency floating-point accumulation and its implementation method. Floating accumulation of this invention comprises a floating-point adder unit, numerous intermediate result buffers, an input control unit and an output control unit. The floating-point accumulation implementation method of this invention is used for gradation of the whole accumulation calculation process to ensure cross execution of accumulation calculation processes and graded storage of intermediate results of accumulation calculation at different levels; meanwhile, the operation in the mode of pure flow line can significantly improve utilization rate of internal floating-point adder, and maintain relatively low latency to output of final results of floating-point accumulation calculation.

Abstract: Embodiments of the present invention provide a method of computing validation coverage of an integrated circuit model, comprising: obtaining a logical structure of a integrated circuit model under validation; searching and recording signal paths in the integrated circuit model under validation based on the logical structure; and computing coverage of validation with respect to the signal paths. According to the technical solution as provided in the embodiments of the present invention, a signal path-based validation coverage may be obtained, thereby providing data regarding validation completeness more accurately.

Abstract: A hinge assembly includes a pivot shaft, a first supporting member, a second supporting member, and a positioning member. The first supporting member is rotatably sleeved on the pivot shaft. A positioning protrusion is formed on the first supporting member. The second supporting member is non-rotatably sleeved on the pivot shaft. The positioning member has an elastic portion and is non-rotatably sleeved on the pivot shaft. A positioning groove receiving the positioning protrusion is defined in a periphery of the positioning member and adjacent to the elastic portion. An LCD device is further provided in the present disclose.

Abstract: A structured interleaving/de-interleaving scheme enables efficient implementation of encoding/decoding based on two-dimensional product codes (2D PC). An encoder has an integrated architecture that performs structured interleaving and PC coding in an integrated manner in which locations in the interleaved data stream are related to row and column indices for the 2D PC coding based on closed-form expressions. In one embodiment, a corresponding decoder implements two-stage low-density parity-check (LDPC) decoding based on the same relationships between locations in the interleaved data stream and row and column indices for the LDPC decoding.