Abstract: Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.

Abstract: Systems and methods for timing-driven shape closure in integrated circuit (“IC”) fabrication are provided. These Integrated Design-Manufacturing Processes (“IDMP”) include a delta flow that integrates information of the IC fabrication timing and geometry verification processes into the IC design. The delta flow is an incremental flow that includes delta-geometry timing prediction processes and/or delta-timing shape prediction processes for processing difference information associated with circuit characterization parameters. The delta flow independently re-characterizes an IC design using the difference or delta information corresponding to the circuit characterization parameters. The delta flow provides delta outputs (incremental) that enhance or re-characterize corresponding parameters of the devices and interconnect structures without the need to generate new circuit characterization parameters and without the need to re-process all information of the IC design.

Abstract: A method of evaluating a stepper process affected by lens aberration is provided. The method includes receiving, from a facilitator responding to a request, a set of optical models including lens aberration information, wherein the lens aberration information is difficult to extract from the optical models. A decision can be made using the set of optical models. The decision could include determining which stepper(s) can be used (or should be avoided) with a mask, a layout, a process, and/or a chemistry. The decision could include ranking a plurality of steppers based on mask data to determine the best stepper (or next best steppers) to use.

Abstract: A method and apparatus for inspecting a photolithography mask for defects is provided. The inspection method comprises providing a defect area image to an image simulator wherein the defect area image is an image of a portion of a photolithography mask, and providing a set of lithography parameters as a second input to the image simulator. The defect area image may be provided by an inspection tool which scans the photolithography mask for defects using a high resolution microscope and captures images of areas of the mask around identified potential defects. The image simulator generates a first simulated image in response to the defect area image and the set of lithography parameters. The first simulated image is a simulation of an image which would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask.

Abstract: Printing very small features on a wafer may require optimizing an illumination configuration in the lithographic imaging system. In a conventional system, an aperture provides only one illumination configuration. In contrast, a programmable aperture can ensure that each mask design is printed using its optimized illumination configuration while minimizing the amount of hardware in the system. The programmable aperture can include a grid of pixels, wherein each pixel can be controlled to provided a predetermined light state. Once installed, the programmable aperture can provide any number of illumination configurations, thereby eliminating the expense of fabricating, testing, and repairing multiple apertures as well as the time associated with installing those multiple apertures.

Abstract: One embodiment of the invention provides a system that facilitates exposing a wafer through at least two masks during an integrated circuit manufacturing process. The system includes a radiation source and two or more illuminators. Each of these illuminators receives radiation from the radiation source, and uses the radiation to illuminate a reticle holder. The radiation that passes through each reticle holder is then combined in an optical combiner, before passing through an imaging optics, which projects the combined radiation onto a semiconductor wafer.

Abstract: A two-dimensional yield map for a device, such as an integrated circuit, in a fabrication facility is computed and associated with layout data for the device in a hierarchical and/or instance-based layout file. The device has a layout including a pattern characterizable by a combination of members of a set of basis shapes. A set of basis pre-images include yield map data representing an interaction of respective members of the set of basis shapes with a defect model. A yield map for the pattern is created by combining basis pre-images corresponding to basis shapes in the combination of members that characterize the pattern to provide a combination result. The output may be displayed as a two dimensional map to an engineer performing yield analysis, or otherwise processed.

Abstract: A method and apparatus for inspecting a photolithography mask for defects is provided. The inspection method comprises providing a defect area image to an image simulator wherein the defect area image is an image of a portion of a photolithography mask, and providing a set of lithography parameters as a second input to the image simulator. The defect area image may be provided by an inspection tool which scans the photolithography mask for defects using a high resolution microscope and captures images of areas of the mask around identified potential defects. The image simulator generates a first simulated image in response to the defect area image and the set of lithography parameters. The first simulated image is a simulation of an image which would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask.

Abstract: An automated metrology recipe set up process is described for a manufacturing process, in which patterns to be formed on a device are defined using a design database. The design database is processed to produce a simulated image of a feature for use in a metrology tool for a measurement of the feature. The simulated image is supplied to the metrology tool, where it is used as a basis for alignment of the tool for the measurement. Other recipe data is combined with the simulated image to provide a fully automated metrology set up process.

Abstract: The present invention uses an instance based (IB) representation to reduce the time required for verifying a transformed layout that was generated from a reference layout. Specifically, an IB based representation is generated from the reference layout. The IB based representation includes sets of instance cells that include a master instance cell and slave instance cells. Only a subset of each set of instance cell needs to be simulated to verify the transformed layout.

Abstract: Serious defects on a mask can compromise the functionality of the integrated circuits formed on the wafer. Nuisance defects, which do not affect the functionality, waste expensive resources. A defect analysis tool with job-based automation can accurately and efficiently determine defect printability. This tool can run a job, using a mask file, to simulate the wafer exposure that the mask would provide under a given set of parameters. These parameters can relate to the mask itself, the inspection system used to create the mask file, and the stepper that can be used to expose the mask. The processes performed during the job can be done uniformly for defects on the mask. This uniformity allows the tool to efficiently run multiple jobs. The results of the job can be presented using different levels of detail to facilitate user review.

Abstract: One embodiment of the invention provides a system that facilitates exposing a wafer through at least two masks during an integrated circuit manufacturing process. The system includes a radiation source and two or more illuminators. Each of these illuminators receives radiation from the radiation source, and uses the radiation to illuminate a reticle holder. The radiation that passes through each reticle holder is then combined in an optical combiner, before passing through an imaging optics, which projects the combined radiation onto a semiconductor wafer.

Abstract: A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.

Abstract: A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.

Abstract: Design geometry information from an area outside the area of interest (AOI) on a mask can be combined with inspection information from the AOI to facilitate an accurate, simulated wafer image. The design geometry information can be easily generated or accessed, thereby ensuring an uninterrupted inspection process and minimizing the associated storage costs for the simulation process. The design geometry information can be pseudo design geometry information or actual design geometry information.

Abstract: The present invention uses an instance based (IB) representation to reduce the time required for verifying a transformed layout that was generated from a reference layout. Specifically, an IB based representation is generated from the reference layout. The IB based representation includes sets of instance cells that include a master instance cell and slave instance cells. Only a subset of each set of instance cell needs to be simulated to verify the transformed layout.

Abstract: A method of evaluating a stepper process affected by lens aberration is provided. The method includes receiving, from a facilitator responding to a request, a set of optical models including lens aberration information, wherein the lens aberration information is difficult to extract from the optical models. A decision can be made using the set of optical models. The decision could include determining which stepper(s) can be used (or should be avoided) with a mask, a layout, a process, and/or a chemistry. The decision could include ranking a plurality of steppers based on mask data to determine the best stepper (or next best steppers) to use.

Abstract: One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. Next, the system converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. The system then performs an further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.

Abstract: Layout processing can be applied to an integrated circuit (IC) layout using a shape-based system. A shape can be defined by a set of associated edges in a specified configuration. A catalog of shapes is defined and layout processing actions are associated with the various shapes. Each layout processing action applies a specified layout modification to its associated shape. A shape-based rule system advantageously enables efficient formulation and precise application of layout modifications. Shapes/actions can be provided as defaults, can be retrieved from a remote source, or can be defined by the user. The layout processing actions can be compiled in a bias table.

Abstract: Automated techniques for identifying dummy/main features on a mask layer are provided. In a multiple mask layer technique, the definition of a dummy/main feature can be based on connectivity information or functional association information. In a geometry technique, the definition of a dummy/main feature can be based on a feature size, a feature shape, a pattern of features, or a proximity of a feature to a neighboring feature. In one embodiment, multiple definitions and multiple techniques can be used.