Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.

Abstract: A semiconductor package includes a first electric integrated circuit component, a second integrated circuit component, and a first plasmonic bridge. The second electric integrated circuit component is aside the first electric integrated circuit component. The first plasmonic bridge is vertically overlapped with both the first electric integrated circuit component and the second electric integrated circuit component. The first plasmonic bridge includes a first plasmonic waveguide optically connecting the first electric integrated circuit component and the second electric integrated circuit component.

Abstract: A semiconductor package includes a first optical transceiver, a second optical transceiver, a third optical transceiver, and a plasmonic waveguide. The first optical transceiver, the second optical transceiver, and the third optical transceiver are stacked in sequential order. The first optical transceiver and the third optical transceiver respectively at least one optical input/output portion for transmitting and receiving an optical signal. The plasmonic waveguide includes a first segment, a second segment, and a third segment optically coupled to one another. The first segment is embedded in the first optical transceiver. The second segment extends through the second optical transceiver. The third segment is embedded in the third optical transceiver. The first segment is optically coupled to the at least one optical input/output portion of the first optical transceiver and the third segment is optically coupled to the at least one optical input/output portion of the third optical transceiver.

Abstract: A method of forming a FinFET device includes following steps. A substrate is provided with a plurality of fins thereon, an isolation layer thereon covering lower portions of the fins, a plurality of dummy strips across the fins, and a dielectric layer aside the dummy strips. The dummy strips is cut to form a trench in the dielectric layer. A first insulating structure is formed in the trench, wherein first and second groups of the dummy strips are beside the first insulating structure. A dummy strip is removed from the first group of the dummy strips to form a first opening that exposes portions of the fins under the dummy strip. The portions of the fins are removed to form a plurality of second openings below the first opening, wherein each second opening has a middle-wide profile. A second insulating structure is formed in the first and second openings.

Abstract: Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and on a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions.

Abstract: A package structure including a plurality of first dies and an insulating encapsulant is provided. The plurality of first dies each include a first waveguide layer having a first waveguide path of a bent pattern, wherein the first waveguide layers of the plurality of first dies are optically coupled to each other to form an optical route. The insulating encapsulant encapsulates the plurality of first dies.

Abstract: A semiconductor package includes a first optical transceiver, a second optical transceiver, a third optical transceiver, and a plasmonic waveguide. The first optical transceiver, the second optical transceiver, and the third optical transceiver are stacked in sequential order. The first optical transceiver and the third optical transceiver respectively at least one optical input/output portion for transmitting and receiving an optical signal. The plasmonic waveguide includes a first segment, a second segment, and a third segment optically coupled to one another. The first segment is embedded in the first optical transceiver. The second segment extends through the second optical transceiver. The third segment is embedded in the third optical transceiver. The first segment is optically coupled to the at least one optical input/output portion of the first optical transceiver and the third segment is optically coupled to the at least one optical input/output portion of the third optical transceiver.

Abstract: A semiconductor package includes a first optical transceiver, a second optical transceiver, a third optical transceiver, and a plasmonic waveguide. The first optical transceiver includes at least one optical input/output portion for transmitting and receiving optical signal. The second optical transceiver is stacked on the first optical transceiver. The third optical transceiver includes at least one optical input/output portion for transmitting and receiving optical signal. The third optical transceiver is stacked on the second optical transceiver. The plasmonic waveguide penetrates through the second optical transceiver and optically couples the at least one optical input/output portion of the first optical transceiver and the at least one optical input/output portion of the third optical transceiver.

Abstract: A method of forming a FinFET device includes following steps. A substrate is provided with a plurality of fins thereon, an isolation layer thereon covering lower portions of the fins, a plurality of dummy strips across the fins, and a dielectric layer aside the dummy strips. The dummy strips is cut to form a trench in the dielectric layer. A first insulating structure is formed in the trench, wherein first and second groups of the dummy strips are beside the first insulating structure. A dummy strip is removed from the first group of the dummy strips to form a first opening that exposes portions of the fins under the dummy strip. The portions of the fins are removed to form a plurality of second openings below the first opening, wherein each second opening has a middle-wide profile. A second insulating structure is formed in the first and second openings.

Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes first fins, second fins, a first gate strip, a second gate strip and a comb-like insulating structure. The first and second fins are disposed on a substrate. The first gate strip is disposed across the first fins. The second gate strip is disposed across the second fins. The comb-like insulating structure is disposed between the first gate strip and the second gate strip and has a plurality of comb tooth parts. In some embodiments, each of the comb tooth parts has a middle-wide profile.

Abstract: A semiconductor package includes a first optical transceiver, a second optical transceiver, a third optical transceiver, and a plasmonic waveguide. The first optical transceiver includes at least one optical input/output portion for transmitting and receiving optical signal. The second optical transceiver is stacked on the first optical transceiver. The third optical transceiver includes at least one optical input/output portion for transmitting and receiving optical signal. The third optical transceiver is stacked on the second optical transceiver. The plasmonic waveguide penetrates through the second optical transceiver and optically couples the at least one optical input/output portion of the first optical transceiver and the at least one optical input/output portion of the third optical transceiver.

Abstract: A package structure including a plurality of first dies and an insulating encapsulant is provided. The plurality of first dies each include a first waveguide layer having a first waveguide path of a bent pattern, wherein the first waveguide layers of the plurality of first dies are optically coupled to each other to form an optical route. The insulating encapsulant encapsulates the plurality of first dies.

Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes first fins, second fins, a first gate strip, a second gate strip and a comb-like insulating structure. The first and second fins are disposed on a substrate. The first gate strip is disposed across the first fins. The second gate strip is disposed across the second fins. The comb-like insulating structure is disposed between the first gate strip and the second gate strip and has a plurality of comb tooth parts. In some embodiments, each of the comb tooth parts has a middle-wide profile.

Abstract: An optical transceiver including a photonic integrated circuit component, an electric integrated circuit component and an insulating encapsulant is provided. The photonic integrated circuit component includes at least one optical input/output portion configured to transmit and receive optical signal. The electric integrated circuit component is disposed on and electrically connected to the photonic integrated circuit component. The insulating encapsulant covers the at least one optical input/output portion of the photonic integrated circuit component. The insulating encapsulant laterally encapsulates the electric integrated circuit component. The insulating encapsulant is optically transparent to the optical signal.

Abstract: A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.

Abstract: A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.

Abstract: A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.

Abstract: Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and on a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions.

Abstract: Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions.

Abstract: Methods of forming silicide contacts in semiconductor devices are presented. An exemplary method comprises providing a semiconductor substrate having an n-type field effect transistor (nFET) region and a p-type field effect transistor (pFET) region; performing a pre-amorphized implantation (PAI) process to an n-type doped silicon (Si) feature in on the nFET region and a p-type doped silicon germanium (SiGe) feature in the pFET region, thereby forming an n-type amorphous silicon (a-Si) feature and a p-type amorphous silicon germanium (a-SiGe) feature; depositing a metal layer over each of the a-Si and a-SiGe features; performing an annealing process on the semiconductor device with a temperature ramp-up rate tuned according to a silicide growth rate difference between the n-type a-Si and the p-type a-SiGe features. During the annealing process the n-type a-Si and the p-type a-SiGe features are completely consumed, and amorphous silicide features are formed in the nFET and pFET regions.