Abstract: A semiconductor memory device has a substrate with a transfer transistor formed thereon. The transfer transistor has drain and source regions with one of the source/drain regions electrically coupled to a charge storage capacitor. The charge storage capacitor includes a trunk-like conducting layer, at least one branch-like conducting layer, a dielectric layer and an upper conducting layer. The trunk-like conducting layer includes a lower trunk section, a middle trunk section and an upper trunk section. One end of the branch-like conducting layer is connected to an internal surface of the trunk-like conducting layer. The branch-like conducting layer together with the trunk-like conducting layer form the storage electrode of the charge storage capacitor. The upper conducting layer serves as an opposing electrode of the charge storage capacitor.

Abstract: A memory cell having a storage capacitor structure which increases the capacitance by adding surface area to the storage electrode of the capacitor. A transfer transistor with a gate electrode and source-drain electrode areas is formed on a semiconductor substrate. An insulating layer is formed on the semiconductor substrate and the transfer transistor, which has a contact opening exposing one of the source-drain electrode areas as a contact area. A storage capacitor is formed on the insulating layer and electrically coupled to the contact area. The storage capacitor includes a first conductive layer with a vertical frame and at least one horizontal plate. The vertical frame is coupled to the contact area through the contact opening and one of the at least one horizontal plates has a plurality of extending areas which extend out vertically. The vertical frame, the at least one horizontal plate and the extending areas together form the storage electrode of the storage capacitor.

Abstract: A method for forming twin-tub wells in a semiconductor substrate is disclosed. The present invention includes forming a first silicon oxide layer on the substrate. A silicon nitride layer is patterned on a portion of the first silicon oxide layer by a photoresist mask. First-type ions are implanted over the substrate not covered by the silicon nitride layer. Next, a second silicon oxide layer formed by a liquid phase deposition method is deposited on a portion of the first silicon oxide layer not covered by the silicon nitride layer. After the silicon nitride layer is removed, second-type ions are implanted over the substrate not covered by the second silicon oxide layer. Finally, the substrate is drived-in such that a first-type well and a second-type well are formed under the first silicon oxide layer.

Abstract: A method of fabricating a semiconductor memory device having a capacitor. First, a first insulating layer is formed on a substrate to cover the transistor. Next, a second insulating layer and a first conductive layer are formed in order. The first conductive layer only covers a portion of the second insulating layer to form a branch-like conductive layer. Then, a third insulating layer is formed. An opening is next formed. A second conductive layer is filled into the opening and therefore electrically connected to the source/drain region of the transistor to form a trunk-like conductive layer. Next, the second and the third insulating layers are removed. After a dielectric film is formed on the exposed surfaces of the first and second conductive layers, a third conductive layer is formed on the dielectric film to form an opposed electrode.

Abstract: A method of fabricating a storage electrode of a storage capacitor of a semiconductor memory device, that includes a substrate, and a transfer transistor formed on the substrate. A first conductive layer is formed connected to the source/drain region. A first insulating layer is then formed over the first conductive layer. A first film is on a portion of the first insulating layer and a second film on the first film, wherein the first film and the second film form a stacked layer, the stacked layer having a sidewall. A second insulating layer is formed on the sidewall of the stacked layer. A third insulating layer is then over the substrate. The second insulating layer and a portion of the first insulating layer therebeneath are removed to form a first opening in the first insulating layer without exposing the first conductive layer. The fourth insulating layer is then removed and a second conductive layer is formed over the substrate and so as to substantially fill the first opening.

Abstract: A method of forming a phase-shift photomask that reduces the defect density, manufacture cost, and fabrication processing time. A transparent layer is prepared. Then a light-transmissive thin film and a light-blocking thin film are successively formed over the transparent layer. Using a photoresist mask, a first anisotropic etch is performed on the wafer to remove exposed parts of the light-transmissive thin film and the light-blocking thin film. An isotropic etch is then performed on the photoresist layer so as to uncover a specific width of an edge part of the light-blocking thin film. Using the etched photoresist layer as a mask, a second anisotropic etch is performed on the light-blocking thin film. The photoresist layer is then removed to form the desired phase-shift photomask.

Abstract: A semiconductor memory device with a tree-type capacitor having increased area for reliable storage thereon of electrical charges representative of data. The tree-type capacitor includes a storage electrode consisting of a trunk-like conductive layer and at least a branch-like conductive layer. The trunk-like conductive layer is electrically coupled to one of the source/drain regions of the transfer transistor in the semiconductor memory device and extends substantially upright. The branch-like conductive layer has one end connected to the trunk-like conductive layer and can be structured in various shapes that allow the branch-like conductive layer to have an increased surface area. A dielectric layer is formed over exposed surfaces of the trunk-like conductive layer and the branch-like conductive layer and an overlaying conductive layer is formed over the dielectric layer which serves as an opposing electrode for the tree-type capacitor.

Abstract: Fabricating a DRAM memory cell with increased capacitance by increasing the surface area of a storage electrode of a storage capacitor includes forming transfer transistor having a gate electrode and source-drain electrode areas on a semiconductor substrate. First, second and third insulating layers are formed in sequence on the semiconductor substrate and the transfer transistor. The third, second and first insulating layers are selectively etched through to form a contact opening exposing one of the source-drain electrode areas as a contact area. An upper portion of the third insulating layer is etched to form a plurality of first trenches. A first conductive layer is formed over the insulating layer filling the contact opening and the first trenches. An upper portion of the first conductive layer is etched to form a plurality of second trenches, and selectively etched to define a pattern area of a storage electrode of a capacitor.

Abstract: A method of fabricating a semiconductor memory device having a transfer transistor and a storage capacitor. First, a first insulating layer is formed on the substrate to cover the transfer transistor. Next, a first conductive layer is formed, which penetrates the first insulating layer and is electrically connected to one of the source/drain regions of the transfer transistor. A pillar-shaped layer is formed on the first conductive layer. At least first and second films are successively formed on the first conductive layer and the pillar-shaped layer. Then, the second film, the first film, and the first conductive layer are patterned to form an opening, exposing the first insulating layer. A second conductive layer is then formed on sidewalls of the opening. The pillar-shaped layer and the first film are then removed. Finally, a dielectric layer is formed on the first and second conductive layers and the second film and a third conductive layer is formed on the dielectric layer.

Abstract: A structure and a method to increase the capacitance of a DRAM capacitor by forming a capacitor electrode with cellular voids to add surface area. According to the method: a transfer transistor with a gate electrode and source-drain electrode regions is formed on a semiconductor substrate. An insulating layer is formed on the semiconductor substrate and the transfer transistor, and the insulating layer is etched to form a contact void for exposing the surface of one of the source-drain electrode areas as a contact. A first conductive layer is formed on the insulating layer and is coupled to the contact through the contact void. On the first conductive layer, at least one middle insulating layer and one middle conductive layer are formed alternately to construct a multiple layer structure. Within the middle insulating layer(s), intercommunicating voids are formed through which the middle conductive layer is coupled to the first conductive layer is coupled to the first conductive layer.

Abstract: A method for minimizing the impurity encroachment effect of the field isolation structures for NMOS, PMOS and CMOS integrated circuits is disclosed. In the process, a first layer and a second layer are deposited on a laminate comprising a substrate having thereon the stacked layers. A photo-resist mask which defines the isolation regions is then formed and the unmasked portion is removed. A third layer is deposited and then is etched anisotropically to form the spacers. A fourth layer is deposited and the chemical-mechanical polishing (CMP) method is applied until the first layer is exposed. After the first layer is removed, the channel-stop ions are implanted, and the spacers are removed for forming the isolation regions by the oxidation. As a result, the channel stop region is self-aligned to the resulting field oxide and the isolation structure is free of the impurity encroachment effect.

Abstract: A method for minimizing the impurity encroachment effect of field isolation structures for NMOS, PMOS and CMOS integrated circuits is disclosed. In the process, a polysilicon layer is deposited on a laminate comprising a substrate having thereon a pad oxide, and the stacked layers on the pad oxide. An overhang layer is deposited on the polysilicon layer, and a photo-resist mask which masks the active regions is then applied so as to remove the unmasked overhang layer and the unmasked polysilicon layer. The resultant structure is isotropically etched to partially undercut the vertical portions of the polysilicon layer under the overhang layer so as to form an overhang. The photo-resist is stripped, and the stacked layers not covered by the overhang layer are etched anisotropically. The channel-stop ions are implanted, and the overhang layer is removed.

Abstract: A method for minimizing the impurity encroachment effect of field isolation structures for NMOS, PMOS and CMOS integrated circuits is disclosed. In the process, a sacrificial layer is deposited on a laminate comprising a substrate having thereon stacked layers. A photo-resist mask which defines the active regions is then formed on the top of the sacrificial layer and an anisotropic etching is used to remove the unmasked sacrificial layer and the stacked layers. A portion of the photo-resist is eroded, and the exposed sacrificial layer is removed. After the photo-resist is removed, channel-stop ions are implanted, and the portion of the stacked layers not covered by the sacrificial layer are etched. After the sacrificial layer is completely removed, isolation regions are formed on the exposed substrate. The channel-stop region is self-aligned to the resulting field oxide and the isolation structure is free of impurity encroachment effect.