Abstract: An electrostatic discharge protection circuit is used in an integrated circuit with a first sub-circuit working with a first working voltage source and a second sub-circuit working with a second working voltage source lower than the first working voltage source. The electrostatic discharge protection circuit includes a first metal-oxide-semiconductor transistor of a first conductive type, having a drain thereof electrically connected to a pad of the integrated circuit, and gate, source and bulk thereof electrically connected to a bulk voltage; and a guard ring of the first conductive type, surrounding the first metal-oxide-semiconductor transistor of the first conductive type and coupled to the second working voltage source.

Abstract: A CMOS structure includes a PMOS portion and an NMOS portion isolated from each other via a P-well region disposed next to the PMOS portion and an N-well region disposed between the P-well region and the NMOS portion, an insulation layer overlying at least the N-well region, and a pad structure disposed over the N-well region. The pad structure further includes: a pad body disposed on the insulation layer; and at least one contact plug penetrating through the insulation layer, having one end coupled to the pad body and the other end coupled to a contact zone in the N-well region; wherein the contact zone is interfaced with the N-well region with P-type dopants.

Abstract: An ESD protection device is described, which includes a P-body region, a P-type doped region, an N-type doped region and an N-sinker region. The P-body region is configured in a substrate. The P-type doped region is configured in the middle of the P-body region. The N-type doped region is configured in the P-body region and surrounds the P-type doped region. The N-sinker region is configured in the substrate and surrounds the P-body region.

Abstract: The Complementary Metal-Oxide Semiconductor (CMOS) transistor of the present invention includes deep halo doped regions in the substrate. The fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains or the source/drain doped regions, and therefore no extra mask is required.

Abstract: A CMOS structure includes a PMOS portion and an NMOS portion isolated from each other via a P-well region disposed next to the PMOS portion and an N-well region disposed between the P-well region and the NMOS portion, an insulation layer overlying at least the N-well region, and a pad structure disposed over the N-well region. The pad structure further includes: a pad body disposed on the insulation layer; and at least one contact plug penetrating through the insulation layer, having one end coupled to the pad body and the other end coupled to a contact zone in the N-well region; wherein the contact zone is interfaced with the N-well region with P-type dopants.

Abstract: An ESD protection device is described, which includes a P-body region, a P-type doped region, an N-type doped region and an N-sinker region. The P-body region is configured in a substrate. The P-type doped region is configured in the middle of the P-body region. The N-type doped region is configured in the P-body region and surrounds the P-type doped region. The N-sinker region is configured in the substrate and surrounds the P-body region.

Abstract: An ESD protection device is described, which includes a first P-type doped region, a second P-type doped region, a first N-type doped region, a second N-type doped region and an isolation structure. The first P-type doped region is configured in a substrate. The second P-type doped region is configured in the first P-type doped region. The first N-type doped region is configured in the first P-type doped region and surrounds the second P-type doped region. The second N-type doped region is configured in the substrate and surrounds the first P-type doped region. The isolation structure is disposed between the first P-type doped region and the second N-type doped region, wherein a spacing is deployed between an outward edge of the first N-type doped region and the isolation structure.

Abstract: The Complementary Metal-Oxide Semiconductor (CMOS) transistor of the present invention includes deep halo doped regions in the substrate. The fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains or the source/drain doped regions, and therefore no extra mask is required.

Abstract: The CMOS transistor of the present invention includes deep halo doped regions in the substrate, which can avoid the occurrence of latch-up. In addition, the fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains or the source/drain doped regions, and therefore no extra mask is required.

Abstract: An ESD protection device is described, which includes a first P-type doped region, a second P-type doped region, a first N-type doped region, a second N-type doped region and an isolation structure. The first P-type doped region is configured in a substrate. The second P-type doped region is configured in the first P-type doped region. The first N-type doped region is configured in the first P-type doped region and surrounds the second P-type doped region. The second N-type doped region is configured in the substrate and surrounds the first P-type doped region. The isolation structure is disposed between the first P-type doped region and the second N-type doped region, wherein a spacing is deployed between an outward edge of the first N-type doped region and the isolation structure.

Abstract: An NMOS device having protection against electrostatic discharge. The NMOS device includes a P-substrate, a P-epitaxial layer overlying the P-substrate, a P-well in the P-epitaxial layer, an N-well in the P-epitaxial layer and encompassing the P-well, an N-Buried Layer (NBL) underneath the P-well and bordering the N-well. The P-well is fully isolated by the N-well and the NBL. The NMOS device further includes a first isolation structure consisting of a gate-insulating layer connected with a field oxide layer, which is formed on the P-epitaxial layer. A gate overlies the first isolation structure. A second isolation structure laterally spaced apart from the first isolation structure is approximately situated on the N-well. An N+ source doping region, which functions as a source of the NMOS device, is disposed in the P-well. An N+ drain doping region, which functions as a drain of the NMOS device, is disposed in the N-well.

Abstract: The CMOS transistor of the present invention includes deep halo doped regions in the substrate, which can avoid the occurrence of latch-up. In addition, the fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains or the source/drain doped regions, and therefore no extra mask is required.

Abstract: The invention provides an ESD protection structure, compatible with the bipolar-CMOS-DMOS (BCD) processes, which provides an enhanced protection performance and better heat dissipation performance. The design of the ESD structures in present invention takes advantage of bipolar punch characteristics of the parasitic bipolar structure to bypass the ESD current, thus significantly reducing the trigger voltage and increasing the ESD protection level. In addition, the ESD protection circuit of the present invention can improve heat dissipation by avoid current crowding near the surface.

Abstract: The invention provides an ESD protection structure, compatible with the bipolar-CMOS-DMOS (BCD) processes, which provides an enhanced protection performance and better heat dissipation performance. The design of the ESD structures in present invention takes advantage of bipolar punch characteristics of the parasitic bipolar structure to bypass the ESD current, thus significantly reducing the trigger voltage and increasing the ESD protection level. In addition, the ESD protection circuit of the present invention can improve heat dissipation by avoid current crowding near the surface.

Abstract: An NMOS device having protection against electrostatic discharge. The NMOS device includes a P-substrate, a P-epitaxial layer overlying the P-substrate, a P-well in the P-epitaxial layer, an N-well in the P-epitaxial layer and encompassing the P-well, an N-Buried Layer (NBL) underneath the P-well and bordering the N-well. The P-well is fully isolated by the N-well and the NBL. The NMOS device further includes a first isolation structure consisting of a gate-insulating layer connected with a field oxide layer, which is formed on the P-epitaxial layer. A gate overlies the first isolation structure. A second isolation structure laterally spaced apart from the first isolation structure is approximately situated on the N-well. An N+ source doping region, which functions as a source of the NMOS device, is disposed in the P-well. An N+ drain doping region, which functions as a drain of the NMOS device, is disposed in the N-well.

Abstract: An NMOS device having protection against electrostatic discharge. The NMOS device includes a P-substrate, a P-epitaxial layer overlying the P-substrate, a P-well in the P-epitaxial layer, an N-well in the P-epitaxial layer and encompassing the P-well, an N-Buried Layer (NBL) underneath the P-well and bordering the N-well. The P-well is fully isolated by the N-well and the NBL. The NMOS device further includes a first isolation structure consisting of a gate-insulating layer connected with a field oxide layer, which is formed on the P-epitaxial layer. A gate overlies the first isolation structure. A second isolation structure laterally spaced apart from the first isolation structure is approximately situated on the N-well. An N+ source doping region, which functions as a source of the NMOS device, is disposed in the P-well. An N+ drain doping region, which functions as a drain of the NMOS device, is disposed in the N-well.