Patents by Inventor Fang Yang

Fang Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11940353
    Abstract: A test device for an automatic pressure regulating valve of an electronic braking system includes a test device composed of an air supply, a pneumatic circuit, a valve, a sensor, a signal processing unit, and a control unit. By subjecting an automatic pressure regulating valve to a bench test including a functional test, a static performance test, a dynamic performance test, an air tightness test, a leakage test, and a brake chamber braking force test, the present disclosure avoids the high risk of a field test, improves the test efficiency, and ensures the test consistency. An automatic pressure regulating valve is tested before being loaded on a vehicle, and parameters of the automatic pressure regulating valve are continuously modified through tests to improve the performance, such that the automatic pressure regulating valve can meet the real-time, fast, independent, and accurate regulation requirements of EBS of commercial vehicles.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: March 26, 2024
    Assignee: Wuhan University Of Technology
    Inventors: Gangyan Li, Hanwei Bao, Jian Hu, Zhiqiang Gu, Fang Yang
  • Patent number: 11943373
    Abstract: An identity certificate may be issued to a blockchain node. The issuance may include issuing a first identity certificate to a first terminal and receiving a second identity certificate issuance request that is from the first terminal. A second identity certificate may be issued to the first terminal, and a third identity certificate issuance request is received from the second terminal. A third identity certificate is issued to the second terminal, so that the second terminal forwards the third identity certificate to the third terminal.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: March 26, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Mao Cai Li, Zong You Wang, Kai Ban Zhou, Chang Qing Yang, Hu Lan, Li Kong, Jin Song Zhang, Yi Fang Shi, Geng Liang Zhu, Qu Cheng Liu, Qiu Ping Chen
  • Publication number: 20240097010
    Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20240096712
    Abstract: Provided is a semiconductor device includes a gate electrode, a gate dielectric layer, a channel layer, an insulating layer, a first source/drain electrode and a second source/drain electrode, a second dielectric layer, and a stop segment. The gate electrode is located within a first dielectric layer that overlies a substrate. The gate dielectric layer is located over the gate electrode. The channel layer is located on the gate dielectric layer. The insulating layer is located over the channel layer. The first source/drain electrode and the second source/drain electrode are located in the insulating layer, and connected to the channel layer. The second dielectric layer is beside one of the first source/drain electrode and the second source/drain electrode. The stop segment is embedded in the second dielectric layer.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Jiang, Chieh-Fang Chen, Yen-Chung Ho, Pin-Cheng Hsu, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240092922
    Abstract: This disclosure relates to anti-TNFRSF9 (tumor necrosis factor receptor superfamily member 9) antibodies, antigen-binding fragments, and the uses thereof.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 21, 2024
    Inventors: Yi Yang, Jingshu Xie, Chunyan Dong, Fang Yang, Chengyuan Lu, Yuelei Shen, Jian Ni, Yanan Guo, Yunyun Chen
  • Publication number: 20240096121
    Abstract: Provided are a computer program product, system, and method for training and using a vector encoder to determine vectors for sub-images of text in an image to subject to optical character recognition. A vector encoder is trained to encode images representing text into vectors in a vector space. Vectors of images representing similar text have a high degree of cohesion in the vector space. Vectors of images representing dissimilar text have a low degree of cohesion in the vector space. An input image is processed to determine sub-images of the input image that bound text represented in the input image. The sub-images are inputted to the vector encoder to output sub-image vectors. The vector encoder generates a search vector for search text. Optical character recognition is applied to at least one region of the input image including the sub-images having sub-image vectors matching the search vector.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Inventors: Zhong Fang YUAN, Tong LIU, Yi Chen ZHONG, Xiang Yu YANG, Guan Chao LI
  • Patent number: 11937426
    Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Ching Chu, Feng-Cheng Yang, Katherine H. Chiang, Chung-Te Lin, Chieh-Fang Chen
  • Publication number: 20240087945
    Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Tsai-Hao HUNG, Ping-Cheng KO, Tzu-Yang LIN, Fang-Yu LIU, Cheng-Han WU
  • Patent number: 11923357
    Abstract: An interfacial structure, along with methods of forming such, are described. The structure includes a first interfacial layer having a first dielectric layer, a first conductive feature disposed in the first dielectric layer, and a first thermal conductive layer disposed on the first dielectric layer. The structure further includes a second interfacial layer disposed on the first interfacial layer. The second interfacial layer is a mirror image of the first interfacial layer with respect to an interface between the first interfacial layer and the second interfacial layer. The second interfacial layer includes a second thermal conductive layer disposed on the first thermal conductive layer, a second dielectric layer disposed on the second thermal conductive layer, and a second conductive feature disposed in the second dielectric layer.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang Cheng, Kuang-Wei Yang, Cherng-Shiaw Tsai, Hsiaokang Chang
  • Patent number: 11901390
    Abstract: A semiconductor device includes a substrate, a dielectric layer, a plurality of dielectric patterns and a conductive pad. The substrate includes a first surface and a second surface opposite to the first surface. The dielectric layer is disposed at the first surface of the substrate, and the substrate is disposed between the dielectric layer and the second surface of the substrate. The dielectric patterns are disposed on the dielectric layer and between the first surface and the second surface of the substrate. The conductive pad is inserted between the plurality of dielectric patterns and extended into the dielectric layer.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chien Ku, Huai-Jen Tung, Keng-Ying Liao, Yi-Hung Chen, Shih-Hsun Hsu, Yi-Fang Yang
  • Patent number: 11901733
    Abstract: Provided are hybrid passive power filter and a three-phase power system. The hybrid passive power filter includes: a series passive harmonic isolation unit, a parallel passive filtering unit, and a harmonic load; the series passive harmonic isolation unit has an input terminal electrically connected to a power grid and an output terminal electrically connected to a first terminal of the harmonic load, and the series passive harmonic isolation unit is configured to isolate harmonics; and the parallel passive filtering unit has an input terminal electrically connected to the output terminal of the series passive harmonic isolation unit and an output terminal electrically connected to a second terminal of the harmonic load, and the parallel passive filtering unit is configured to filter out harmonics.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: February 13, 2024
    Assignee: QINGYUAN POWER SUPPLY BUREAU OF GUANGDONG POWER GRID CORPORATION
    Inventors: Fang Yang, Xiaoliang Tang, Yabing Zhou, Wanyu Ye
  • Patent number: 11808904
    Abstract: An experimental system for out-of-plane seismic performance of a masonry block wall, comprising: a static test bed (1), a lateral limiting system disposed on one side on the static test bed (1), and a transverse load system disposed on the other side on the static test bed (1), a masonry block wall to be tested (401) being disposed between the lateral limiting system and the transverse load system. The experimental system also comprises a vertical load system disposed above a wall.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: November 7, 2023
    Assignee: NANJING GONGDA CONSTRUCTION TECHNOLOGY CO., LTD.
    Inventors: Yanqin Liu, Zhanggen Guo, Yuqiang Xiong, Haipeng Xu, Fang Yang
  • Patent number: 11786217
    Abstract: The invention provides an intra-needle ultrasound system and its method of use for analysis, tracking, and display of pleura in millimeter-scale resolution. This method includes the following steps: Assembling the puncture needle and intra-needle ultrasound transducer, which can generate and receive ultrasound waves at the needle tip. To transform the axial ultrasonic signal into a figure, that can help to identify different anatomic structures according to the corresponding feature of ultrasonic RF (Radio Frequency) signal, and to set the region of interest according to corresponding RF feature of amplitude and depth. This invention can indicate the distance between the ultrasound needle tip and pleura in a real-time fashion, and to identify the best position for anesthetic injection in the paravertebral block (PVB) and the intercostals nerve block (ICNB). The system can also help to avoid damage to the pleura and lung during the nerve block procedure.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: October 17, 2023
    Assignees: NATIONAL YANG MING CHIAO TUNG UNIVERSITY, TAIPEI VETERANS GENERAL HOSPITAL
    Inventors: Huihua Chiang, Chien-Kun Ting, Shu-Wei Liao, Fu-Wei Su, Ching-Fang Yang, Chia-Wei Yang
  • Publication number: 20230288591
    Abstract: An experimental system for out-of-plane seismic performance of a masonry block wall, comprising: a static test bed (1), a lateral limiting system disposed on one side on the static test bed (1), and a transverse load system disposed on the other side on the static test bed (1), a masonry block wall to be tested (401) being disposed between the lateral limiting system and the transverse load system. The experimental system also comprises a vertical load system disposed above a wall.
    Type: Application
    Filed: April 19, 2021
    Publication date: September 14, 2023
    Applicant: NANJING GONGDA CONSTRUCTION TECHNOLOGY CO., LTD.
    Inventors: Yanqin LIU, Zhanggen GUO, Yuqiang Xiong, Haipeng XU, Fang Yang
  • Publication number: 20230272067
    Abstract: The present invention relates to anti-TIGIT antibodies and antigen-binding fragments thereof that bind to both human TIGIT and mouse TIGIT. The present application also provides are nucleotides encoding the antibodies or fragments thereof, compositions or combinations comprising the antibodies or fragments thereof, and uses of the antibodies or fragments thereof in treatment of immune-related disease such as cancers and viral infection.
    Type: Application
    Filed: June 23, 2021
    Publication date: August 31, 2023
    Inventors: Jianhua SUI, Fang YANG, Linlin ZHAO, Zhizhong WEI
  • Publication number: 20230272109
    Abstract: Provided are an antibody targeting Claudin 18.2, an antibody-drug conjugate, and use thereof in treatment of cancer. Also provided are a nucleotide encoding the Claudin 18.2 antibody, a polynucleotide combination, an expression vector, an expression vector combination, a pharmaceutical composition comprising the Caudill 18.2 antibody and the antibody-drug conjugate, and an application thereof in preparation of a medication for treatment or prevention of cancer.
    Type: Application
    Filed: May 7, 2022
    Publication date: August 31, 2023
    Inventors: Jianmin FANG, Yuanhao LI, Marie M. ZHU, Jing JIANG, Yuelei SHEN, Shenjun LI, Wenting LUO, Xiaoping ZHANG, Lili WANG, Ling WANG, Qinbin ZHANG, Fang YANG
  • Patent number: 11742648
    Abstract: Provided is an on-line ice-melting apparatus. The apparatus is configured for melting the ice on a three-phase line. The apparatus includes an adjustable reactor, a grounding transformer, a controller, and an auxiliary circuit. The grounding transformer, the adjustable reactor, the auxiliary circuit, and a line of any phase of the three-phase line form a first control loop. The adjustable reactor includes a working winding, a control winding, and a short-circuit winding. The working winding is connected between the grounding transformer and the auxiliary circuit. The controller is electrically connected to the control winding and the short-circuit winding separately.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 29, 2023
    Assignee: QINGYUAN POWER SUPPLY BUREAU OF GUANGDONG POWER GRID CORPORATION
    Inventors: Xiaoliang Tang, Fang Yang, Yabing Zhou, Weibin Jiang, Kaihong Li
  • Patent number: 11736515
    Abstract: The present invention relates to a reconfigurable switch forwarding engine parser capable of disabling hardware Trojans. The parser comprises a data preprocessing unit, several cascaded basic processing units and an extraction unit, wherein a key path of a basic processing unit of the first stage extracts and shifts a key bit keyword of a key, and sends a result to a data path of the current stage and a key path of the next stage; basic processing units of other stages carry out keyword extraction and shifting on a key frame and the data frame in sequence; and the extraction unit extracts the key frame and the data frame from a basic processing unit of the last stage, and forwards same to a subsequent packet processing part. The present invention can be widely applied to the design of the switch forwarding engine parser.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: August 22, 2023
    Assignee: TSINGHUA UNIVERSITY
    Inventors: XiangYu Li, Fang Yang
  • Patent number: 11692891
    Abstract: An apparatus for testing a pressure change rate of a component in an electro-pneumatic braking system of a commercial vehicle includes a pressure change rate test bench, a pneumatic loop configured to implement on-off control of air and detection on a pressure change rate of a tested component in an electro-pneumatic braking system of a commercial vehicle, a signal processing unit configured to acquire a pressure signal and a differential pressure signal and perform analog-digital conversion on the signals to provide signals recognizable by an upper controller and a lower execution component, and a control unit configured to communicate with the pneumatic loop and drive the components in the pneumatic loop to act by setting a control parameter to obtain test data of the tested component in the electro-pneumatic braking system of the commercial vehicle in the pneumatic loop.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: July 4, 2023
    Assignee: Wuhan University Of Technology
    Inventors: Jian Hu, Yi Cheng, Hanwei Bao, Fang Yang, Gangyan Li
  • Publication number: 20230196737
    Abstract: An image recognition method and an electronic apparatus configured for image recognition are provided. A training sample set is provided to train a recognition model including neural networks to recognize a classification label to which an image to be tested belongs through the trained recognition model. The training sample set includes image sets respectively belonging to users. During the training process, training images corresponding to classification labels are obtained from a first image set in the training sample set as reference images for training; a training image is obtained from a second image set different from the first image set as an input image for training; the reference images for training and the input image for training are obtained as inputs to the neural networks for training. The input to each neural network includes at least one of the reference images for training and the input image for training.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 22, 2023
    Applicants: Industrial Technology Research Institute, Taichung Veterans General Hospital
    Inventors: Yu-An Chiou, Yueh-Se Li, Shih-Fang Yang Mao, Wen-Cheng Chao, Sou-Jen Shih, Shu-Fang Liu, Hui-Jiun Chen, Chieh-Liang Wu