Abstract: A method of generating a power network layout is provided. A first conductive line, generated by a processor, is in a first conductive layer along a first direction. A plurality of second conductive lines, generated by a processor, is in a second conductive layer along a second direction, substantially vertical to the first direction. The second conductive lines overlap with the first conductive line. A first plurality of interlayer vias, generated by a processor, is interposed between the first conductive layer and the second conductive layer at where the second conductive lines overlapping the first conductive line. Each of the second conductive lines has a width such that a first routing track adjacent to the first conductive line is available for routing or a second routing track adjacent to one of the plurality of second conductive lines is available for routing.

Abstract: In some embodiments, a fishbone structure in a power network includes a first conductive segment in a first conductive layer running in a first direction, a plurality of second conductive segments in a second conductive layer running in a second direction and a plurality of interlayer vias between the first conductive layer and the second conductive layer. The second direction is substantially vertical to the first direction. The plurality of second conductive segments overlap with the first conductive segment. The plurality of interlayer vias are formed at where the plurality of second conductive segments overlap with the first conductive segment. Each of the plurality of second conductive segments has a width such that the first conductive segment has a first unit spacing with a first adjacent conductive line or one of the plurality of second conductive segments has a second unit spacing with a second adjacent conductive line.

Abstract: A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further includes a second ILD layer disposed over the first ILD layer, and a second conductive layer including a second plurality of conductive lines formed in the second ILD layer. At least one conductive line of the second plurality of conductive lines is formed adjacent to at least one conductive line of the first plurality of conductive lines. The at least one conductive line of the second plurality of conductive lines contacts the at least one conductive line of the first plurality of conductive lines at an interface.

Abstract: An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.

Abstract: In some embodiments, a fishbone structure in a power network includes a first conductive segment in a first conductive layer running in a first direction, a plurality of second conductive segments in a second conductive layer running in a second direction and a plurality of interlayer vias between the first conductive layer and the second conductive layer. The second direction is substantially vertical to the first direction. The plurality of second conductive segments overlap with the first conductive segment. The plurality of interlayer vias are formed at where the plurality of second conductive segments overlap with the first conductive segment. Each of the plurality of second conductive segments has a width such that the first conductive segment has a first unit spacing with a first adjacent conductive line or one of the plurality of second conductive segments has a second unit spacing with a second adjacent conductive line.

Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.

Abstract: A method includes comparing one or more cells to a selection guideline and storing the cells that meet the selection guideline in a non-transient computer readable storage medium to create the cell library based on the comparing. The selection guideline identifies a suitable position of a boundary pin within a cell.

Abstract: A method includes comparing one or more cells to a selection guideline and storing the cells that meet the selection guideline in a non-transient computer readable storage medium to create the cell library based on the comparing. The selection guideline identifies a suitable position of a boundary pin within a cell.

Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.

Abstract: A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first conductive layer, the second conductive layer including a second plurality of conductive lines extending in a second direction. The device further includes a self-aligned interconnect formed at an interface where a first conductive line of the first plurality of conductive lines is in electrical contact with a first conductive line of the second plurality of conductive lines. The device further includes a blocking portion interposed between a second conductive line of the first plurality of conductive lines and a second conductive line of the second plurality of conductive lines.

Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.

Abstract: A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first conductive layer, the second conductive layer including a second plurality of conductive lines extending in a second direction. The device further includes a self-aligned interconnect formed at an interface where a first conductive line of the first plurality of conductive lines is in electrical contact with a first conductive line of the second plurality of conductive lines. The device further includes a blocking portion interposed between a second conductive line of the first plurality of conductive lines and a second conductive line of the second plurality of conductive lines.

Abstract: A multilayer device and method for fabricating a multilayer device is disclosed. An exemplary multilayer device includes a substrate, a first interlayer dielectric (ILD) layer disposed over the substrate, and a first conductive layer including a first plurality of conductive lines formed in the first ILD layer. The device further includes a second ILD layer disposed over the first ILD layer, and a second conductive layer including a second plurality of conductive lines formed in the second ILD layer. At least one conductive line of the second plurality of conductive lines is formed adjacent to at least one conductive line of the first plurality of conductive lines. The at least one conductive line of the second plurality of conductive lines contacts the at least one conductive line of the first plurality of conductive lines at an interface.

Abstract: An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.

Abstract: A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved.

Abstract: A method of forming an integrated circuit structure includes forming a first and a second plurality of tracks parallel to a first direction and on a wafer representation. The first and the second plurality of tracks are allocated in an alternating pattern. A first plurality of patterns is laid out on the first plurality of tracks and not on the second plurality of tracks. A second plurality of patterns is laid out on the second plurality of tracks and not on the first plurality of tracks. The first plurality of patterns is extended in the first direction and in a second direction perpendicular to the first direction, so that each of the second plurality of patterns is surrounded by portions of the first plurality of patterns, and substantially none of neighboring ones of the first plurality of patterns on the wafer representation have spacings greater than a pre-determined spacing.

Abstract: A method and apparatus for achieving multiple patterning compliant technology design layouts is provided. An exemplary method includes providing a routing grid having routing tracks; designating each of the routing tracks one of at least two colors; applying a pattern layout having a plurality of features to the routing grid, wherein each of the plurality of features corresponds with at least one routing track; and applying a feature splitting constraint to determine whether the pattern layout is a multiple patterning compliant layout. If the pattern layout is not a multiple patterning compliant layout, the pattern layout may be modified until a multiple patterning compliant layout is achieved.

Abstract: A method of forming an integrated circuit structure includes forming a first and a second plurality of tracks parallel to a first direction and on a wafer representation. The first and the second plurality of tracks are allocated in an alternating pattern. A first plurality of patterns is laid out on the first plurality of tracks and not on the second plurality of tracks. A second plurality of patterns is laid out on the second plurality of tracks and not on the first plurality of tracks. The first plurality of patterns is extended in the first direction and in a second direction perpendicular to the first direction, so that each of the second plurality of patterns is surrounded by portions of the first plurality of patterns, and substantially none of neighboring ones of the first plurality of patterns on the wafer representation have spacings greater than a pre-determined spacing.