Abstract: A compact ADC circuit can include one or more comparators, and a serial DAC (Digital-to-Analog) circuit that provides a signal to the comparator (or comparators). In addition, the ADC circuit can include a serial DAC redistribution sequencer that can provide a plurality of signals as input to the serial DAC circuit and is subject to a redistribution cycle and which receives as input a signal from a data multiplexer whose input connects electronically to an output of the comparator. The circuit can further include an ADC code register that provides an ADC output that connects electronically to the output of the comparator and the input to the data multiplexer. Shared logic circuitry for sharing common logic between pixels can be included, wherein the shared logic circuitry connects electronically to the data multiplexer and the ADC code register, wherein the shared logic circuitry promotes area and power savings for the pixel detector circuit.

Abstract: A compact ADC circuit can include one or more comparators, and a serial DAC (Digital-to-Analog) circuit that provides a signal to the comparator (or comparators). In addition, the ADC circuit can include a serial DAC redistribution sequencer that can provide a plurality of signals as input to the serial DAC circuit and is subject to a redistribution cycle and which receives as input a signal from a data multiplexer whose input connects electronically to an output of the comparator. The circuit can further include an ADC code register that provides an ADC output that connects electronically to the output of the comparator and the input to the data multiplexer. Shared logic circuitry for sharing common logic between pixels can be included, wherein the shared logic circuitry connects electronically to the data multiplexer and the ADC code register, wherein the shared logic circuitry promotes area and power savings for the pixel detector circuit.

Abstract: A compact ADC circuit can include one or more comparators, and a serial DAC (Digital-to-Analog) circuit that provides a signal to the comparator (or comparators). In addition, the ADC circuit can include a serial DAC redistribution sequencer that can provide a plurality of signals as input to the serial DAC circuit and is subject to a redistribution cycle and which receives as input a signal from a data multiplexer whose input connects electronically to an output of the comparator. The circuit can further include an ADC code register that provides an ADC output that connects electronically to the output of the comparator and the input to the data multiplexer. Shared logic circuitry for sharing common logic between pixels can be included, wherein the shared logic circuitry connects electronically to the data multiplexer and the ADC code register, wherein the shared logic circuitry promotes area and power savings for the pixel detector circuit.

Abstract: A detecting apparatus includes a multi-tier 3D integrated ASIC comprising one or more analog tiers and one or more digital tiers, and a sensor bonded to the multi-tier 3D integrated ASIC. The detecting apparatus includes an electrical substrate and a group of FPGAs or custom data management ASICs. The detecting apparatus also includes a thermal management system, a power distribution system and one or more connectors to transfer data to a data acquisition system configured for radiation spectroscopy or imaging with zero suppressed or full frame readout.

Abstract: A compact ADC circuit can include one or more comparators, and a serial DAC (Digital-to-Analog) circuit that provides a signal to the comparator (or comparators). In addition, the ADC circuit can include a serial DAC redistribution sequencer that can provide a plurality of signals as input to the serial DAC circuit and is subject to a redistribution cycle and which receives as input a signal from a data multiplexer whose input connects electronically to an output of the comparator. The circuit can further include an ADC code register that provides an ADC output that connects electronically to the output of the comparator and the input to the data multiplexer. Shared logic circuitry for sharing common logic between pixels can be included, wherein the shared logic circuitry connects electronically to the data multiplexer and the ADC code register, wherein the shared logic circuitry promotes area and power savings for the pixel detector circuit.

Abstract: A three dimensional integrated edgeless pixel detector apparatus can be implemented, which includes a multi-tiered three-dimensional detector having one sensor layer, and two ASIC layers comprising an analog tier and a digital tier configured for x-ray photon time of arrival measurement and imaging. In a preferred embodiment, a hit processor can be implemented in association with a priority encoder and a configuration register and output serializer with mode selection.

Abstract: A detecting apparatus includes a multi-tier 3D integrated ASIC comprising one or more analog tiers and one or more digital tiers, and a sensor bonded to the multi-tier 3D integrated ASIC. The detecting apparatus includes an electrical substrate and a group of FPGAs or custom data management ASICs. The detecting apparatus also includes a thermal management system, a power distribution system and one or more connectors to transfer data to a data acquisition system configured for radiation spectroscopy or imaging with zero suppressed or full frame readout.

Abstract: A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

Abstract: A detecting apparatus includes a multi-tier 3D integrated ASIC comprising one or more analog tiers and one or more digital tiers, and a sensor bonded to the multi-tier 3D integrated ASIC. The detecting apparatus includes an electrical substrate and a group of FPGAs or custom data management ASICs. The detecting apparatus also includes a thermal management system, a power distribution system and one or more connectors to transfer data to a data acquisition system configured for radiation spectroscopy or imaging with zero suppressed or full frame readout.

Abstract: A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

Abstract: A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

Abstract: A three dimensional integrated edgeless pixel detector apparatus can be implemented, which includes a multi-tiered three-dimensional detector having one sensor layer, and two ASIC layers comprising an analog tier and a digital tier configured for x-ray photon time of arrival measurement and Imaging. In a preferred embodiment, a hit processor can be implemented in association with a priority encoder and a configuration register and output serializer with mode selection.

Abstract: A detecting apparatus includes a multi-tier 3D integrated ASIC comprising one or more analog tiers and one or more digital tiers, and a sensor bonded to the multi-tier 3D integrated ASIC. The detecting apparatus includes an electrical substrate and a group of FPGAs or custom data management ASICs. The detecting apparatus also includes a thermal management system, a power distribution system and one or more connectors to transfer data to a data acquisition system configured for radiation spectroscopy or imaging with zero suppressed or full frame readout.

Abstract: A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.