Patents by Inventor Farasoa Nathalie ETONO

Farasoa Nathalie ETONO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DESIGN FOR TESTABILITY CIRCUITRY PLACEMENT WITHIN AN INTEGRATED CIRCUIT DESIGN
    Publication number: 20230205960
    Abstract: Generating an integrated circuit (IC) includes receiving Design For Testability (DFT) Compressor Decompressor (CODEC) circuitry of an integrated circuit (IC) design, and partitioning the DFT CODEC circuitry into two or more sub-blocks based on a number of scan chains within the IC design. Further, scan chains are assigned to each of the two or more sub-blocks based on locations of end points within the scan chains. A layout of the IC design is generated by placing the DFT CODEC circuitry within the IC design based the locations of end points within the scan chains and the assigned scan chains to each of the two or more sub-blocks.
    Type: Application
    Filed: December 29, 2022
    Publication date: June 29, 2023
    Inventors: Farasoa Nathalie ETONO, Rajeev MURGAI, Daniel Eugenio DURÁN, Manoj GUPTA, Suryanarayana DUGGIRALA, Menno Ewout VERBEEK, Tihomir SOKCEVIC