Abstract: A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through. the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

Abstract: A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

Abstract: A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

Abstract: TTL circuits are described for generating from an input signal complementary output signals useful in integrated circuit applications. For an enable gate, an alternate enable transistor element is coupled in emitter follower configuration in the enable gate with the base of the alternate enable transistor coupled to follow the enable gate input signal E and provide through the emitter circuit an alternate enable signal A complementary to the enable signal E. The complementary enable signals are applied in an improved TTL tristate output device with reduced output capacitance. The alternate enable signal A is coupled to the base of an active discharge transistor element at the base of the pull-down transistor of the tristate input device for actively discharging and diverting Miller feedback current caused by transitions on the common bus output when the enable signal E is at low potential and the device is in the high impedance third state.