Patents by Inventor Farhana Sheikh
Farhana Sheikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11983530Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to process data associated with a variety of matrix dimensions using one or more complex number operations, one or more real number operations, or both. Configurations may be applied to the configurable circuitry to program the configurable circuitry for a next operation. The configurable circuitry may process data according to a variety of operations based at least in part on operation of a repeated processing element coupled in a compute network of processing elements.Type: GrantFiled: March 27, 2020Date of Patent: May 14, 2024Assignee: Intel CorporationInventors: Sumeet Singh Nagi, Farhana Sheikh, Scott Jeremy Weber, Uneeb Yaqub Rathore
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Publication number: 20220407549Abstract: A receiver circuit associated with a communication device is disclosed. The receiver circuit comprises a digital data compression circuit configured to receive a plurality of digital receive signals derived from a plurality of analog receive signals respectively associated with the receiver circuit. The digital data compression circuit is further configured to compress the plurality of digital receive signals to form one or more compressed digital data signals based thereon, to be provided to an input output (I/O) interface associated therewith. In some embodiments, a compressed digital signal dimension associated with the one or more compressed digital data signals is less than a digital signal dimension associated with the plurality of digital receive signals.Type: ApplicationFiled: August 23, 2022Publication date: December 22, 2022Inventors: Oner Orhan, Hosein Nikopour, Peter Sagazio, Farhana Sheikh, Junyoung Nam, Shilpa Talwar
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Patent number: 11444645Abstract: A receiver circuit associated with a communication device is disclosed. The receiver circuit comprises a digital data compression circuit configured to receive a plurality of digital receive signals derived from a plurality of analog receive signals respectively associated with the receiver circuit. The digital data compression circuit is further configured to compress the plurality of digital receive signals to form one or more compressed digital data signals based thereon, to be provided to an input output (I/O) interface associated therewith. In some embodiments, a compressed digital signal dimension associated with the one or more compressed digital data signals is less than a digital signal dimension associated with the plurality of digital receive signals.Type: GrantFiled: January 2, 2018Date of Patent: September 13, 2022Assignee: Apple Inc.Inventors: Oner Orhan, Hosein Nikopour, Peter Sagazio, Farhana Sheikh, Junyoung Nam, Shilpa Talwar
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Patent number: 11205749Abstract: A spintronic device includes a first ferromagnetic layer. The first ferromagnetic layer includes a first direction of magnetic polarization. Furthermore, the spintronic device includes a second ferromagnetic layer. The second ferromagnetic layer includes a second direction of magnetic polarization opposite to the first direction. Furthermore, the spintronic device includes a long spin lifetime layer. Furthermore, the spintronic device includes a first tunnel barrier layer disposed between the first ferromagnetic layer and the long spin lifetime layer. Furthermore, the spintronic device includes a second tunnel barrier layer disposed between the second ferromagnetic layer and the long spin lifetime layer.Type: GrantFiled: March 23, 2017Date of Patent: December 21, 2021Assignee: Intel CorporationInventors: Richard Dorrance, Farhana Sheikh
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Publication number: 20210075456Abstract: A receiver circuit associated with a communication device is disclosed. The receiver circuit comprises a digital data compression circuit configured to receive a plurality of digital receive signals derived from a plurality of analog receive signals respectively associated with the receiver circuit. The digital data compression circuit is further configured to compress the plurality of digital receive signals to form one or more compressed digital data signals based thereon, to be provided to an input output (I/O) interface associated therewith. In some embodiments, a compressed digital signal dimension associated with the one or more compressed digital data signals is less than a digital signal dimension associated with the plurality of digital receive signals.Type: ApplicationFiled: January 2, 2018Publication date: March 11, 2021Inventors: Oner Orhan, Hosein Nikopour, Peter Sagazio, Farhana Sheikh, Junyoung Nam, Shilpa Talwar
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Patent number: 10742278Abstract: An orthogonalization matrix calculation circuit may include a scaling coefficient calculation circuit configured to calculate a scaling coefficient for each of a plurality of candidate update operations for the orthogonalization matrix, wherein each of the plurality of candidate update operations comprises combining linearly at least one of a first column or a second column of the orthogonalization matrix previously utilized to update the orthogonalization matrix, an update operation selection circuit configured to select an optimum candidate update operation from the plurality of candidate update operations, and a matrix update circuit configured to update the orthogonalization matrix according to the scaling coefficient of the optimum candidate update operation.Type: GrantFiled: October 30, 2015Date of Patent: August 11, 2020Assignee: Apple Inc.Inventors: Farhana Sheikh, Alexios Konstantinos Balatsoukas Stimming
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Publication number: 20200225947Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to process data associated with a variety of matrix dimensions one or more complex number operations, one or more real number operations, or both. Configurations may be applied to the configurable circuitry to program the configurable circuitry for a next operation. The configurable circuitry may process data according to a variety of operations based at least in part on operation of a repeated processing element coupled in a compute network of processing elements.Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Inventors: Sumeet Singh Nagi, Farhana Sheikh, Scott Jeremy Weber, Uneeb Yaqub Rathore
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Patent number: 10713333Abstract: A calculation circuit for calculating a transform of an input sequence may include a plurality of butterfly computation circuits configured to perform a plurality of butterfly computations and to produce a plurality of outputs during each of a plurality of computation stages, a wired routing network configured to route a first plurality of outputs of the plurality of butterfly computation circuits from a first computation stage of the plurality of computation stages as input to the plurality of butterfly computation circuits during a second computation stage of the plurality of computation stages according to a reconfigurable routing configuration, and routing control circuitry configured to modify the reconfigurable routing configuration for a third computation stage of the plurality of computation stages.Type: GrantFiled: December 21, 2015Date of Patent: July 14, 2020Assignee: Apple Inc.Inventors: Farhana Sheikh, Ankit Sharma, Jaydeep Kulkarni
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Patent number: 10673461Abstract: A pipeline decoding system for performing pipelined decoding of a codeword characterized by one or more parity checks may include a first pipeline stage circuit configured to process a first parity set composed of one or more first parity checks of the codeword and to process a second parity set composed of one or more second parity checks of the codeword, a second pipeline stage circuit configured to generate one or more codeword update messages for the second parity set based on a first estimate of the codeword, and a third pipeline stage circuit configured to update the first estimate of the codeword with one or more codeword update messages for the first parity set to obtain a second estimate of the codeword.Type: GrantFiled: December 24, 2015Date of Patent: June 2, 2020Assignee: INTEL CORPORATIONInventors: Chia-Hsiang Chen, Wei Tang, Farhana Sheikh
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Publication number: 20200020850Abstract: A spintronic device includes a first ferromagnetic layer. The first ferromagnetic layer includes a first direction of magnetic polarization. Furthermore, the spintronic device includes a second ferromagnetic layer. The second ferromagnetic layer includes a second direction of magnetic polarization opposite to the first direction. Furthermore, the spintronic device includes a long spin lifetime layer. Furthermore, the spintronic device includes a first tunnel barrier layer disposed between the first ferromagnetic layer and the long spin lifetime layer. Furthermore, the spintronic device includes a second tunnel barrier layer disposed between the second ferromagnetic layer and the long spin lifetime layer.Type: ApplicationFiled: March 23, 2017Publication date: January 16, 2020Inventors: Richard Dorrance, Farhana Sheikh
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Patent number: 10361739Abstract: The disclosure generally relates to a method, apparatus and system for identifying non-compliant radio emissions and for enforcing compliance. In one embodiment, the disclosure relates to a dynamic radiation control of a radio by measuring a signal attribute for an outbound signal having a protocol; comparing the signal attribute with a predefined mask, the predefined mask governed by at least one of a radio location or a signal protocol; and determining whether to transmit the outbound signal.Type: GrantFiled: December 8, 2017Date of Patent: July 23, 2019Assignee: Intel CorporationInventors: Hossein Alavi, Farhana Sheikh, Markus Dominik Mueck, Vladimir Ivanov
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Publication number: 20180351575Abstract: A pipeline decoding system for performing pipelined decoding of a codeword characterized by one or more parity checks may include a first pipeline stage circuit configured to process a first parity set composed of one or more first parity checks of the codeword and to process a second parity set composed of one or more second parity checks of the codeword, a second pipeline stage circuit configured to generate one or more codeword update messages for the second parity set based on a first estimate of the codeword, and a third pipeline stage circuit configured to update the first estimate of the codeword with one or more codeword update messages for the first parity set to obtain a second estimate of the codeword.Type: ApplicationFiled: December 24, 2015Publication date: December 6, 2018Inventors: Chia-Hsiang CHEN, Wei TANG, Farhana SHEIKH
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Publication number: 20180336161Abstract: A calculation circuit for calculating a transform of an input sequence may include a plurality of butterfly computation circuits configured to perform a plurality of butterfly computations and to produce a plurality of outputs during each of a plurality of computation stages, a wired routing network configured to route a first plurality of outputs of the plurality of butterfly computation circuits from a first computation stage of the plurality of computation stages as input to the plurality of butterfly computation circuits during a second computation stage of the plurality of computation stages according to a reconfigurable routing configuration, and routing control circuitry configured to modify the reconfigurable routing configuration for a third computation stage of the plurality of computation stages.Type: ApplicationFiled: December 21, 2015Publication date: November 22, 2018Inventors: Farhana SHEIKH, Ankit SHARMA, Jaydeep KULKARNI
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Publication number: 20180287675Abstract: An orthogonalization matrix calculation circuit may include a scaling coefficient calculation circuit configured to calculate a scaling coefficient for each of a plurality of candidate update operations for the orthogonalization matrix, wherein each of the plurality of candidate update operations comprises combining linearly at least one of a first column or a second column of the orthogonalization matrix previously utilized to update the orthogonalization matrix, an update operation selection circuit configured to select an optimum candidate update operation from the plurality of candidate update operations, and a matrix update circuit configured to update the orthogonalization matrix according to the scaling coefficient of the optimum candidate update operation.Type: ApplicationFiled: October 30, 2015Publication date: October 4, 2018Inventors: Farhana Sheikh, Alexios Konstantinos Balatsoukas Stimming
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Publication number: 20180262224Abstract: The disclosure generally relates to a method, apparatus and system for identifying non-compliant radio emissions and for enforcing compliance. In one embodiment, the disclosure relates to a dynamic radiation control of a radio by measuring a signal attribute for an outbound signal having a protocol; comparing the signal attribute with a predefined mask, the predefined mask governed by at least one of a radio location or a signal protocol; and determining whether to transmit the outbound signal.Type: ApplicationFiled: December 8, 2017Publication date: September 13, 2018Applicant: Intel CorporationInventors: Hossein Alavi, Farhana Sheikh, Markus Dominik Mueck, Vladimir Ivanov
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Patent number: 10002654Abstract: In some embodiments, disclosed is a wordline boosting technique using a self-timed capacitive charge boosting approach.Type: GrantFiled: June 26, 2015Date of Patent: June 19, 2018Assignee: Intel CorporationInventors: Jaydeep P Kulkarni, Pramod Kolar, Ankit Sharma, Subho Chatterjee, Karthik Subramanian, Farhana Sheikh, Wei-Hsiang Ma
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Patent number: 9967820Abstract: According to the present disclosure, a communication device configured to power on a main receiver to receive data from a network includes: a low power receiver configured to receive a wake up packet, including a preamble, from the network and oversample the wake up packet; a circuit arrangement including: a correlator configured to correlate the oversampled portion of the preamble; a delay and adder configured to take an output of the correlator, delay the output of the correlator, and add the output of the correlator back onto itself to produce a delay output; a peak detector configured to detect a peak pattern in the delay output; a demodulator configured to calculate a decoding threshold value to produce a demodulated data; and a packet parser configured to check the demodulated data for a data set in order to selectively output a nonzero signal to power on the main receiver.Type: GrantFiled: June 29, 2016Date of Patent: May 8, 2018Assignee: Intel CorporationInventors: Richard Dorrance, Minyoung Park, Alexander W. Min, Farhana Sheikh
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Patent number: 9935615Abstract: An adaptation hardware accelerator comprises a calculation unit to receive inputs at predefined time interval(s) that correspond to a calculation iteration, the inputs associated with adaptive filters having taps, and determine correlation and cross-correlation data based thereon for a given iteration. The correlation data comprises a correlation matrix. Determining the matrix comprises determining submatrices in an upper triangular portion and a diagonal portion of the matrix. The accelerator comprises an adaptation core unit to determine adaptive weights associated with the adaptive filters, respectively, based on an adaptive algorithm, utilizing the correlation and cross correlation data. The accelerator unit comprises a convergence detector unit to determine a convergence parameter; and a controller to generate an iteration signal for each time interval based on the parameter.Type: GrantFiled: September 22, 2015Date of Patent: April 3, 2018Assignee: Intel CorporationInventors: Farhana Sheikh, Ching-En Lee, Feng Xue, Anuja S. Vaidya, Eduardo X. Alban, Albert Oskar Filip Andersson, Chia-Hsiang Chen, Shu-Ping Yeh
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Patent number: 9893746Abstract: A polynomial kernel generator is configured to mitigate nonlinearity in a receiver path from a transmitter path comprising a nonlinear component in a communication device or system. The polynomial kernel generator operates to generate polynomial kernels that can be utilized to model the nonlinearity as a function of a piecewise polynomial approximation applied to a nonlinear function of the nonlinearity. The polynomial kernel generator generates kernels in a multiplier less architecture with polynomial computations in a log domain using a fixed number of adders.Type: GrantFiled: June 25, 2015Date of Patent: February 13, 2018Assignee: Intel CorporationInventors: Farhana Sheikh, Ching-En Lee, Shu-Ping Yeh, Feng Xue, Anuja Surendra Vaidya
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Publication number: 20180007629Abstract: According to the present disclosure, a communication device configured to power on a main receiver to receive data from a network includes: a low power receiver configured to receive a wake up packet, including a preamble, from the network and oversample the wake up packet; a circuit arrangement including: a correlator configured to correlate the oversampled portion of the preamble; a delay and adder configured to take an output of the correlator, delay the output of the correlator, and add the output of the correlator back onto itself to produce a delay output; a peak detector configured to detect a peak pattern in the delay output; a demodulator configured to calculate a decoding threshold value to produce a demodulated data; and a packet parser configured to check the demodulated data for a data set in order to selectively output a nonzero signal to power on the main receiver.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Inventors: Richard DORRANCE, Minyoung PARK, Alexander W. MIN, Farhana SHEIKH