Abstract: A method and data processing system for detecting tampering of a machine learning model is provided. The method includes training a machine learning model. During a training operating period, a plurality of input values is provided to the machine learning model. In response to a predetermined invalid input value, the machine learning model is trained that a predetermined output value will be expected. The model is verified that it has not been tampered with by inputting the predetermined invalid input value during an inference operating period. If the expected output value is provided by the machine learning model in response to the predetermined input value, then the machine learning model has not been tampered with. If the expected output value is not provided, then the machine learning model has been tampered with. The method may be implemented using the data processing system.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: Smart sensors comprising one or more microelectromechanical systems (MEMS) sensors and a digital signal processor (DSP) in a sensor package are described. An exemplary smart sensor can comprise a MEMS acoustic sensor or microphone and a DSP housed in a package or enclosure comprising a substrate and a lid and a package substrate that defines a back cavity for the MEMS acoustic sensor or microphone. Provided implementations can also comprise a MEMS motion sensor housed in the package or enclosure. Embodiments of the subject disclosure can provide improved power management and battery life from a single charge by intelligently responding to trigger events or wake events while also providing an always on sensor that persistently detects the trigger events or wake events. In addition, various physical configurations of smart sensors and MEMS sensor or microphone packages are described.

Abstract: Smart sensors comprising one or more microelectromechanical systems (MEMS) sensors and a digital signal processor (DSP) in a sensor package are described. An exemplary smart sensor can comprise a MEMS acoustic sensor or microphone and a DSP housed in a package or enclosure comprising a substrate and a lid and a package substrate that defines a back cavity for the MEMS acoustic sensor or microphone. Provided implementations can also comprise a MEMS motion sensor housed in the package or enclosure. Embodiments of the subject disclosure can provide improved power management and battery life from a single charge by intelligently responding to trigger events or wake events while also providing an always on sensor that persistently detects the trigger events or wake events. In addition, various physical configurations of smart sensors and MEMS sensor or microphone packages are described.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: Smart sensors comprising one or more microelectromechanical systems (MEMS) sensors and a digital signal processor (DSP) in a sensor package are described. An exemplary smart sensor can comprise a MEMS acoustic sensor or microphone and a DSP housed in a package or enclosure comprising a substrate and a lid and a package substrate that defines a back cavity for the MEMS acoustic sensor or microphone. Provided implementations can also comprise a MEMS motion sensor housed in the package or enclosure. Embodiments of the subject disclosure can provide improved power management and battery life from a single charge by intelligently responding to trigger events or wake events while also providing an always on sensor that persistently detects the trigger events or wake events. In addition, various physical configurations of smart sensors and MEMS sensor or microphone packages are described.

Abstract: Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally, or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: A method and data processing system for detecting tampering of a machine learning model is provided. The method includes training a machine learning model. During a training operating period, a plurality of input values is provided to the machine learning model. In response to a predetermined invalid input value, the machine learning model is trained that a predetermined output value will be expected. The model is verified that it has not been tampered with by inputting the predetermined invalid input value during an inference operating period. If the expected output value is provided by the machine learning model in response to the predetermined input value, then the machine learning model has not been tampered with. If the expected output value is not provided, then the machine learning model has been tampered with. The method may be implemented using the data processing system.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: Providing security features in an audio sensor is presented herein. A micro-electro-mechanical system (MEMS) microphone can include an acoustic membrane that converts an acoustic signal into an electrical signal; an electronic amplifier that increases an amplitude of the electrical signal to generate an amplified signal; and switch(es) configured to prevent propagation of a direct current (DC) voltage source to the MEMS microphone; prevent propagation of the DC voltage source to the electronic amplifier; prevent propagation of the electrical signal to the electronic amplifier; and/or prevent propagation of the amplified signal to an external device.

Abstract: Providing security features in an audio sensor is presented herein. A micro-electro-mechanical system (MEMS) microphone can include an acoustic membrane that converts an acoustic signal into an electrical signal; an electronic amplifier that increases an amplitude of the electrical signal to generate an amplified signal; and switch(es) configured to prevent propagation of a direct current (DC) voltage source to the MEMS microphone; prevent propagation of the DC voltage source to the electronic amplifier; prevent propagation of the electrical signal to the electronic amplifier; and/or prevent propagation of the amplified signal to an external device.

Abstract: Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally, or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: Systems and techniques for providing improved beam forming functionality and/or improve noise cancellation functionality in a microphone package are presented. In an implementation, a device includes a first microelectromechanical systems (MEMS) sensor, a second MEMS sensor, and a digital signal processor. The first MEMS sensor is contained in a first back cavity within the device. The second MEMS sensor is contained in a second back cavity within the device. The digital signal processor generates a cardioid microphone pattern based on data associated with the first MEMS sensor contained in the first back cavity and other data associated with the second MEMS sensor contained in the second back cavity, where the digital signal processor forms at least a portion of the first back cavity and the second back cavity.

Abstract: Systems and methods that protect CMOS layers from exposure to a release chemical are provided. The release chemical is utilized to release a micro-electro-mechanical (MEMS) device integrated with the CMOS wafer. Sidewalls of passivation openings created in a complementary metal-oxide-semiconductor (CMOS) wafer expose a dielectric layer of the CMOS wafer that can be damaged on contact with the release chemical. In one aspect, to protect the CMOS wafer and prevent exposure of the dielectric layer, the sidewalls of the passivation openings can be covered with a metal barrier layer that is resistant to the release chemical. Additionally or optionally, an insulating barrier layer can be deposited on the surface of the CMOS wafer to protect a passivation layer from exposure to the release chemical.