Patents by Inventor Farid Nemati
Farid Nemati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180314592Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.Type: ApplicationFiled: July 9, 2018Publication date: November 1, 2018Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
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Patent number: 10042701Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.Type: GrantFiled: September 22, 2016Date of Patent: August 7, 2018Assignee: Apple Inc.Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
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Patent number: 9691465Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.Type: GrantFiled: November 20, 2015Date of Patent: June 27, 2017Assignee: Micron Technology, Inc.Inventors: Farid Nemati, Scott T. Robins, Rajesh N. Gupta
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Publication number: 20170091026Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.Type: ApplicationFiled: September 22, 2016Publication date: March 30, 2017Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
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Patent number: 9520447Abstract: Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.Type: GrantFiled: June 16, 2015Date of Patent: December 13, 2016Assignee: Micron Technology, Inc.Inventors: Rajesh N. Gupta, Farid Nemati
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Patent number: 9472279Abstract: A memory system and dynamic memory cell programming process thereof is disclosed. The dynamic programming processes comprises the processes of: (a) determining a concurrent-programmable bit number in accordance with a current budget limit; (b) identifying, with a memory controller, a memory cell in a plurality of memory cells in need of programming; (c) performing programming operation on at least one of the memory cells in need of programming; (d) detecting, with a write-detection unit, an programming operation status of the memory cell being programmed and correspondingly generating a program completion indication; and (e) triggering programming operation to a subsequent one of the memory cells according to the program completion indication from the write-detection unit.Type: GrantFiled: January 20, 2015Date of Patent: October 18, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yi-Chun Shih, Farid Nemati
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Publication number: 20160211018Abstract: A memory system and dynamic memory cell programming process thereof is disclosed. The dynamic programming processes comprises the processes of: (a) determining a concurrent-programmable bit number in accordance with a current budget limit; (b) identifying, with a memory controller, a memory cell in a plurality of memory cells in need of programming; (c) performing programming operation on at least one of the memory cells in need of programming; (d) detecting, with a write-detection unit, an programming operation status of the memory cell being programmed and correspondingly generating a program completion indication; and (e) triggering programming operation to a subsequent one of the memory cells according to the program completion indication from the write-detection unit.Type: ApplicationFiled: January 20, 2015Publication date: July 21, 2016Inventors: YI-CHUN SHIH, FARID NEMATI
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Patent number: 9361966Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.Type: GrantFiled: August 1, 2013Date of Patent: June 7, 2016Assignee: Micron Technology, Inc.Inventors: Farid Nemati, Scott T. Robins, Rajesh N. Gupta
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Publication number: 20160078917Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.Type: ApplicationFiled: November 20, 2015Publication date: March 17, 2016Inventors: Farid Nemati, Scott T. Robins, Rajesh N. Gupta
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Publication number: 20150311254Abstract: Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.Type: ApplicationFiled: June 16, 2015Publication date: October 29, 2015Inventors: Rajesh N. Gupta, Farid Nemati
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Patent number: 9082494Abstract: Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.Type: GrantFiled: January 13, 2012Date of Patent: July 14, 2015Assignee: Micron Technology, Inc.Inventors: Rajesh N. Gupta, Farid Nemati
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Publication number: 20150155283Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.Type: ApplicationFiled: February 4, 2015Publication date: June 4, 2015Inventors: Rajesh N. Gupta, Farid Nemati, Scott T. Robins
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Patent number: 8952418Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.Type: GrantFiled: March 1, 2011Date of Patent: February 10, 2015Assignee: Micron Technology, Inc.Inventors: Rajesh N. Gupta, Farid Nemati, Scott T. Robins
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Publication number: 20130314986Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.Type: ApplicationFiled: August 1, 2013Publication date: November 28, 2013Applicant: Micron Technology, Inc.Inventors: Farid Nemati, Scott T. Robins, Rajesh N. Gupta
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Patent number: 8576607Abstract: An integrated circuit and methods of operating same are described. In an embodiment of the integrated circuit included is an array of memory cells, where each of the memory cells includes a resistance-change storage element and a thyristor-based storage element coupled in series. In embodiments of the methods included are methods for data transfer, data tracking, and operating a memory array.Type: GrantFiled: June 29, 2011Date of Patent: November 5, 2013Inventor: Farid Nemati
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Patent number: 8576649Abstract: Sense amplifiers and operations thereof are described. More particularly, embodiments of integrated circuit having a sense amplifier coupled to a first bitline and a second bitline of a memory array are described. The sense amplifier generally includes: a latch circuit and a group select input/output circuit, as well as read, reference voltage, and precharge circuitry. Further described is an embodiment of a method for a refresh operation. First data states of a group of memory cells of an array are read and written back as second data states without changing voltages at sense nodes of the latch circuits from the reading, where the second data states are an inverse of the first data states.Type: GrantFiled: June 29, 2011Date of Patent: November 5, 2013Inventor: Farid Nemati
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Patent number: 8519431Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.Type: GrantFiled: March 8, 2011Date of Patent: August 27, 2013Assignee: Micron Technology, Inc.Inventors: Farid Nemati, Scott T. Robins, Rajesh N. Gupta
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Publication number: 20130182486Abstract: Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.Type: ApplicationFiled: January 13, 2012Publication date: July 18, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Rajesh N. Gupta, Farid Nemati
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Patent number: 8441881Abstract: Method and integrated circuit for tracking for read and inverse write back of a group of thyristor-based memory cells is described. The method includes: reading the group of memory cells to obtain read data, and writing back opposite data states for the read data to the group of memory cells. The group of memory cells includes data cells and at least one check cell for check data, where the check data indicates polarity of the read data. The integrated circuit includes a grouping of memory cells of an array of memory cells including data cells and at least one check cell, and sense amplifiers. The at least one check cell is to track inversion/non-inversion status of the data cells associated therewith, and the sense amplifiers are coupled to obtain read information from the grouping and to write back data states opposite of those of the read information.Type: GrantFiled: June 29, 2011Date of Patent: May 14, 2013Assignee: T-RAM SemiconductorInventor: Farid Nemati
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Publication number: 20120228629Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.Type: ApplicationFiled: March 8, 2011Publication date: September 13, 2012Applicant: Micron Technology, Inc.Inventors: Farid Nemati, Scott T. Robins, Rajesh N. Gupta