Abstract: Efficient scan system presented can comprise: an array including a plurality of array non scannable components and a plurality of array quasi-scannable components wherein each column of the array includes at least one of the plurality of array quasi-scannable components; and an input interface configured to receive and selectively forward data and scan information to at least a portion of the array. At least a portion of the plurality of array quasi-scannable components can form a diagonal pattern in the array. The input interface can include: an input interface selection component wherein an output of the input interface selection component is communicatively coupled to an input of the input interface quasi-scannable component associated with one row and an input of the input interface selection component is communicatively coupled to an output of one of the plurality of array quasi-scannable components associated with another row.

Abstract: Efficient scan system presented can comprise: an array including a plurality of array non scannable components and a plurality of array quasi-scannable components wherein each column of the array includes at least one of the plurality of array quasi-scannable components; and an input interface configured to receive and selectively forward data and scan information to at least a portion of the array. At least a portion of the plurality of array quasi-scannable components can form a diagonal pattern in the array. The input interface can include: an input interface selection component wherein an output of the input interface selection component is communicatively coupled to an input of the input interface quasi-scannable component associated with one row and an input of the input interface selection component is communicatively coupled to an output of one of the plurality of array quasi-scannable components associated with another row.

Abstract: A series of secondary or “shadow” storage elements are employed that duplicate, or “shadow”, the information in a circuit's core logic shadowed functional registers. These shadow storage elements are then coupled to form a separate, independently-addressable shadow scan path. The information contained in the shadowed functional registers of a circuit is then shifted out via the shadow scan path without altering the shadowed functional registers using special commands issued from a JTAG controller.

Abstract: Internally generating test vectors on a microchip during a burnin stage allows for better toggle coverage while not requiring external memory. A test access port (TAP) controller which accepts signals from a user and indicates to a linear feedback shift register (LFSR) that the microchip is in the burnin stage. The LFSR then may generate a set of pseudorandom values using a polynomial. The values are then shifted one per clock cycle into the internal scan chain of flips-flops on the chip, which toggles the internal state of the chip. New pseudorandom values are also generated one-by-one during the shift. By using this approach, the internal states of the chip are toggled without the use of an external memory for the burnin system.

Abstract: A series of secondary or “shadow” storage elements are employed that duplicate, or “shadow”, the information in a circuit's core logic primary storage elements. These shadow storage elements are then coupled to form a separate, independently-addressable shadow scan path. The information contained in the primary storage elements is then scanned out via the shadow scan path without altering the primary storage elements using special commands issued from a JTAG controller. This shadow scan system allows a circuit to remain operational while a snapshot of the core logic information is scanned out.

Abstract: A series of secondary or “shadow” storage elements are employed that duplicate, or “shadow”, the information in a circuit's core logic primary storage elements. These shadow storage elements are then coupled to form a separate, independently-addressable shadow scan path. The information contained in the primary storage elements is then scanned out via the shadow scan path without altering the primary storage elements using special commands issued from a JTAG controller. This shadow scan system allows a circuit to remain operational while a snapshot of the core logic information is scanned out.

Abstract: Disclosed herein is a system and method for determining whether multiplexers select lines within a circuit are exclusive of one another. The disclosed invention may be performed in an automated manner on one or more multiplexers within subunit, across subunits, within units, across units, or within entire modules. The method and system employs the application of logical circuit analysis in combination with predefined gate logic to ascertain select line exclusivity in an automated and flexible fashion.

Abstract: A system for coupling a Dynamic Termination Logic (DTL) type output driver to IEEE 1149.1 boundary-scan circuitry includes a logic circuit that converts the data and output enable signals of the IEEE 1149.1 specification to test “q_up,” “q_dn” and “q25_dn” signals meeting the requirements of the DTL driver. These test q_up, q_dn and q25_dn are selectively provided to the DTL driver during boundary-scan testing of the output driver. In a further refinement, the system also converts functional q_up, q_dn and q25_dn signals provided by the circuit under test to the data and output enable signals of the IEEE 1149.1 specification. The system allows the widely used IEEE 1149.1 boundary-scan standard to be used with DTL drivers. The resulting compatibility simplifies the testing and use of the DTL drivers, and provides a new boundary-scan standard for use with DTL drivers that is compliant with the IEEE 1149.1 standard.

Abstract: A circuit for coupling a LIC driver to a IEEE 1149.1 boundary scan implementation includes a logic circuit that converts the data and oe signals of the IEEE 1149.1 specification to test "q.sub.-- up" and "q.sub.-- dn" signals meeting the requirements of the LIC driver. These test "q.sub.-- up" and "q.sub.-- dn" signals are selectively provided to the LIC driver during boundary scan testing of the output driver. In a further refinement, the logic circuit also converts functional q.sub.-- up and q.sub.-- dn signals provided by the circuit under test to the data and oe signals of the IEEE 1149.1 specification. The logic circuit allows the widely used IEEE 1149.1 boundary scan standard to be used with LIC drivers. The resulting compatibility simplifies the testing and use of the LIC drivers, and provides a new boundary scan standard for use with LIC drivers that is compliant with the IEEE 1149.1 standard.

Abstract: A method for coupling a linear impedance control (LIC) type output driver to IEEE 1149.1 boundary scan circuitry includes entering a boundary scan load mode to load a test pattern into a chain of boundary scan registers (BSRs). The test pattern includes values corresponding to output enable and data signals according to the IEEE 1149.1 standard. Then these data and output enable signals from the BSRs are converted into test "q.sub.-- up" and "q.sub.-- dn" signals meeting the requirements of the LIC driver. These test "q.sub.-- up" and "q.sub.-- dn" signals are selectively provided to the LIC driver during boundary scan testing of the LIC driver. In a further refinement, the method enters a boundary scan capture mode to capture the response (i.e., the functional q.sub.-- up and q.sub.-- dn signals) of the circuit under test to input test patterns shifted into the BSRs. The functional q.sub.-- up and q.sub.-- dn signals are converted into response data and oe signals complying with the IEEE 1149.