Abstract: A circuit structure and a method for supressing single event transients (SETs) or glitches in digital electronic circuits are provided. The circuit includes a first input which receives an output of a digital electronic circuit and a second input which receives a redundant or duplicated output of the digital electronic circuit. The circuit includes only four two-input gates of two different kinds selected from AND, OR, NAND and NOR gates. The four two-input gates being arranged so that a final circuit output is impervious to a change in a logic level of only the first input or only the second input, and the final circuit output is equivalent to the logic level of the first and second inputs when the logic level of the first and second inputs match.

Abstract: A circuit structure (200) for suppressing single event transients (SETs) or glitches in digital electronic circuits is provided. The circuit structure includes a first input (100) which receives an output of a digital electronic circuit (A), a second input (100?) which receives a redundant or duplicated output of the digital electronic circuit (A?), and two sub-circuits (102, 106) that each receive the inputs and have one output. One of the sub-circuits is insensitive to a change in the value of one of its inputs when the inputs are in a first logic state and the other sub-circuit is insensitive to a change in the value of one of the inputs when the inputs are in a second, inverted logic state. The sub-circuit outputs are input into a two-input multiplexer (202) which has its output (204) connected to its selection port (SEL), and the sub-circuits are arranged so that the sub-circuit which is insensitive to a change in the value of one of its inputs is selected whenever the output of the multiplexer changes.

Abstract: A circuit structure (200) for suppressing single event transients (SETs) or glitches in digital electronic circuits is provided. The circuit structure includes a first input (100) which receives an output of a digital electronic circuit (A), a second input (100?) which receives a redundant or duplicated output of the digital electronic circuit (A?), and two sub-circuits (102, 106) that each receive the inputs and have one output. One of the sub-circuits is insensitive to a change in the value of one of its inputs when the inputs are in a first logic state and the other sub-circuit is insensitive to a change in the value of one of the inputs when the inputs are in a second, inverted logic state. The sub-circuit outputs are input into a two-input multiplexer (202) which has its output (204) connected to its selection port (SEL), and the sub-circuits are arranged so that the sub-circuit which is insensitive to a change in the value of one of its inputs is selected whenever the output of the multiplexer changes.