Patents by Inventor Farrell Good
Farrell Good has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8980752Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.Type: GrantFiled: July 22, 2013Date of Patent: March 17, 2015Assignee: Micron Technology, Inc.Inventors: Farrell Good, Baosuo Zhou, Xiaolong Fang, Fatma Arzum Simsek-Ege
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Publication number: 20130309858Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.Type: ApplicationFiled: July 22, 2013Publication date: November 21, 2013Applicant: Micron Technology, Inc.Inventors: Farrell Good, Baosuo Zhou, Xiaolong Fang, Fatma Arzum Simsek-Ege
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Patent number: 8492278Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.Type: GrantFiled: March 30, 2010Date of Patent: July 23, 2013Assignee: Micron Technology, Inc.Inventors: Farrell Good, Baosuo Zhou, Xiaolong Fang, Fatma Arzum Simsek-Ege
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Patent number: 8476002Abstract: Some embodiments include methods in which spaced-apart first features are formed from a first material having a reflow temperature. Second material is formed along sidewalls of the first features, and third material is formed over the second material and the first features. The third material may be formed at a temperature above the reflow temperature of the first material, and the second material may support the first features so that the first features do not collapse even though they are exposed to such temperature. In some embodiments the third material has an undulating topography. Fourth material may be formed within the valleys of the undulating topography, and subsequently the first features may be removed together with at least some of the third material to leave a pattern comprising second features formed from the second material and pedestals formed from the fourth material.Type: GrantFiled: September 10, 2012Date of Patent: July 2, 2013Assignee: Micron Technology, Inc.Inventors: Zishu Zhang, Anton J. deVilliers, Robert Carr, Farrell Good
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Patent number: 8450164Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.Type: GrantFiled: February 22, 2010Date of Patent: May 28, 2013Assignee: Micron Technology, Inc.Inventors: Vishwanath Bhat, Kevin R. Shea, Farrell Good
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Publication number: 20130004889Abstract: Some embodiments include methods in which spaced-apart first features are formed from a first material having a reflow temperature. Second material is formed along sidewalls of the first features, and third material is formed over the second material and the first features. The third material may be formed at a temperature above the reflow temperature of the first material, and the second material may support the first features so that the first features do not collapse even though they are exposed to such temperature. In some embodiments the third material has an undulating topography. Fourth material may be formed within the valleys of the undulating topography, and subsequently the first features may be removed together with at least some of the third material to leave a pattern comprising second features formed from the second material and pedestals formed from the fourth material.Type: ApplicationFiled: September 10, 2012Publication date: January 3, 2013Applicant: MICRON TECHNOLOGY, INC.Inventors: Zishu Zhang, Anton deVilliers, Robert Carr, Farrell Good
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Patent number: 8318578Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated.Type: GrantFiled: October 7, 2009Date of Patent: November 27, 2012Assignee: Micron Technology, Inc.Inventors: Kevin Shea, Brett Busch, Farrell Good, Irina Vasilyeva, Vishwanath Bhat
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Patent number: 8288083Abstract: Some embodiments include methods in which spaced-apart first features are formed from a first material having a reflow temperature. Second material is formed along sidewalls of the first features, and third material is formed over the second material and the first features. The third material may be formed at a temperature above the reflow temperature of the first material, and the second material may support the first features so that the first features do not collapse even though they are exposed to such temperature. In some embodiments the third material has an undulating topography. Fourth material may be formed within the valleys of the undulating topography, and subsequently the first features may be removed together with at least some of the third material to leave a pattern comprising second features formed from the second material and pedestals formed from the fourth material.Type: GrantFiled: November 5, 2010Date of Patent: October 16, 2012Assignee: Micron Technology, Inc.Inventors: Zishu Zhang, Anton deVilliers, Robert Carr, Farrell Good
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Publication number: 20120115074Abstract: Some embodiments include methods in which spaced-apart first features are formed from a first material having a reflow temperature. Second material is formed along sidewalls of the first features, and third material is formed over the second material and the first features. The third material may be formed at a temperature above the reflow temperature of the first material, and the second material may support the first features so that the first features do not collapse even though they are exposed to such temperature. In some embodiments the third material has an undulating topography. Fourth material may be formed within the valleys of the undulating topography, and subsequently the first features may be removed together with at least some of the third material to leave a pattern comprising second features formed from the second material and pedestals formed from the fourth material.Type: ApplicationFiled: November 5, 2010Publication date: May 10, 2012Inventors: Zishu Zhang, Anton deVilliers, Robert Carr, Farrell Good
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Publication number: 20110244674Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.Type: ApplicationFiled: March 30, 2010Publication date: October 6, 2011Inventors: Farrell Good, Baosuo Zhou, Xiaolong Fang, Fatma Arzum Simsek-Ege
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Publication number: 20100151653Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.Type: ApplicationFiled: February 22, 2010Publication date: June 17, 2010Applicant: Micron Technology, Inc.Inventors: Vishwanath Bhat, Kevin R. Shea, Farrell Good
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Patent number: 7682924Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.Type: GrantFiled: August 13, 2007Date of Patent: March 23, 2010Assignee: Micron Technology, Inc.Inventors: Vishwanath Bhat, Kevin R. Shea, Farrell Good
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Publication number: 20100025362Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated.Type: ApplicationFiled: October 7, 2009Publication date: February 4, 2010Applicant: Micron Technology, Inc.Inventors: Kevin Shea, Brett Busch, Farrell Good, Irina Vasilyeva, Vishwanath Bhat
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Patent number: 7618874Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated.Type: GrantFiled: May 2, 2008Date of Patent: November 17, 2009Assignee: Micron Technology, Inc.Inventors: Kevin Shea, Brett Busch, Farrell Good, Irina Vasilyeva, Vishwanath Bhat
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Publication number: 20090275185Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated.Type: ApplicationFiled: May 2, 2008Publication date: November 5, 2009Inventors: Kevin Shea, Brett Busch, Farrell Good, Irina Vasilyeva, Vishwanath Bhat
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Publication number: 20090047769Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.Type: ApplicationFiled: August 13, 2007Publication date: February 19, 2009Inventors: Vishwanath Bhat, Kevin R. Shea, Farrell Good
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Publication number: 20070117381Abstract: Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using the silicon rich barrier layers. Methods of forming the semiconductor devices and memory cells are also provided.Type: ApplicationFiled: January 23, 2007Publication date: May 24, 2007Applicant: Micron Technology, Inc.Inventors: Sanh Tang, Chris Braun, Farrell Good
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Publication number: 20060205135Abstract: Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using the silicon rich barrier layers. Methods of forming the semiconductor devices and memory cells are also provided.Type: ApplicationFiled: May 9, 2006Publication date: September 14, 2006Inventors: Sanh Tang, Chris Braun, Farrell Good
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Publication number: 20050026378Abstract: Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using the silicon rich barrier layers. Methods of forming the semiconductor devices and memory cells are also provided.Type: ApplicationFiled: August 30, 2004Publication date: February 3, 2005Inventors: Sanh Tang, Chris Braun, Farrell Good
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Patent number: 6537910Abstract: A metal suicide film and method of forming the same are provided. The method comprises depositing metal silicide layers onto a substrate assembly with alternating layers of silicon. The resulting metal silicide film has a disrupted grain structure and smaller grain sizes than prior art films of the same thickness, which increases the resistance of the material to stress cracks in subsequent thermal processing and reduces the overall residual stress of the material.Type: GrantFiled: October 27, 2000Date of Patent: March 25, 2003Assignee: Micron Technology, Inc.Inventors: Robert Burke, Farrell Good, Anand Srinivasan