Patents by Inventor Fataneh Ghodrat
Fataneh Ghodrat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996166Abstract: A technique for processing computer instructions is provided. The technique includes obtaining information for an instruction state memory entry for an instruction; identifying, for the instruction state memory entry, a slot in an instruction state memory having selectably powered rows and blocks, based on clustering criteria; and placing the instruction state memory entry into the identified slot.Type: GrantFiled: August 29, 2019Date of Patent: May 28, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Fataneh Ghodrat, Tien E. Wei
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Publication number: 20240160478Abstract: An apparatus to facilitate increasing processing resources in processing cores of a graphics environment is disclosed. The apparatus includes a plurality of processing resources to execute one or more execution threads; a plurality of message arbiter-processing resource (MA-PR) routers, wherein a respective MA-PR router of the plurality of MA-PR routers corresponds to a pair of processing resources of the plurality of processing resources and is to arbitrate routing of a thread control message from a message arbiter between the pair of processing resources; a plurality of local shared cache (LSC) sequencers to provide an interface between at least one LSC of the processing core and the plurality of processing resources; and a plurality of instruction caches (ICs) to store instructions of the one or more execution threads, wherein a respective IC of the plurality of ICs interfaces with a portion of the plurality of processing resources.Type: ApplicationFiled: November 15, 2022Publication date: May 16, 2024Applicant: Intel CorporationInventors: Jiasheng Chen, Chunhui Mei, Ben J. Ashbaugh, Naveen Matam, Joydeep Ray, Timothy Bauer, Guei-Yuan Lueh, Vasanth Ranganathan, Prashant Chaudhari, Vikranth Vemulapalli, Nishanth Reddy Pendluru, Piotr Reiter, Jain Philip, Marek Rudniewski, Christopher Spencer, Parth Damani, Prathamesh Raghunath Shinde, John Wiegert, Fataneh Ghodrat
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Patent number: 11720499Abstract: A graphics pipeline includes a texture cache having cache lines that are partitioned into a plurality of subsets. The graphics pipeline also includes one or more compute units that selectively generates a miss request for a first subset of the plurality of subsets of a cache line in the texture cache in response to a cache miss for a memory access request to an address associated with the first subset of the cache line. In some embodiments, the cache lines are partitioned into a first sector and a second sector. The compute units generate miss requests for the first sector, and bypass generating miss requests for the second sector, in response to cache misses for memory access requests received during a request cycle being in the first sector.Type: GrantFiled: December 28, 2020Date of Patent: August 8, 2023Assignees: Advanced Micro Devices, Inc., SAMSUNG ELECTRONICS CO., LTD.Inventors: Fataneh Ghodrat, Stephen W. Somogyi, Zhenhong Liu
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Patent number: 11393156Abstract: Techniques for performing ray tracing for a ray are provided. The techniques include, based on first traversal of a bounding volume hierarchy, identifying a first memory page that is classified as resident, obtaining a first portion of the bounding volume hierarchy associated with the first memory page, traversing the first portion of the bounding volume hierarchy according to a ray intersection test, based on second traversal of the bounding volume hierarchy, identifying a second memory page that is classified as valid and non-resident, and in response to the second memory page being classified as valid and non-resident, determining that a miss occurs for each node of the bounding volume hierarchy within the second memory page.Type: GrantFiled: March 13, 2020Date of Patent: July 19, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Skyler Jonathon Saleh, Fataneh Ghodrat
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Publication number: 20220206950Abstract: A graphics pipeline includes a texture cache having cache lines that are partitioned into a plurality of subsets. The graphics pipeline also includes one or more compute units that selectively generates a miss request for a first subset of the plurality of subsets of a cache line in the texture cache in response to a cache miss for a memory access request to an address associated with the first subset of the cache line. In some embodiments, the cache lines are partitioned into a first sector and a second sector. The compute units generate miss requests for the first sector, and bypass generating miss requests for the second sector, in response to cache misses for memory access requests received during a request cycle being in the first sector.Type: ApplicationFiled: December 28, 2020Publication date: June 30, 2022Inventors: Fataneh GHODRAT, Stephen W. SOMOGYI, Zhenhong LIU
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Publication number: 20220171717Abstract: A system includes a memory implementing one or more virtual queues and a processor coupled to the memory. In response to issuing one or more requests for data, a processor maps one or more of the requests for data to a return queue structure. The processor then allocates one or more virtual queues to the return queue structure based on the mapped requests. In response to allocating the virtual queues to the return queue, the processor writes the data indicated in the mapped requests to the allotted virtual queues and enables the return queue for arbitration. When the return queue is enabled for arbitration, the processor reads out the data written to the allocated virtual queues, processes the read out data, and provides the processed data to a processing pipeline.Type: ApplicationFiled: December 1, 2021Publication date: June 2, 2022Inventor: Fataneh GHODRAT
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Publication number: 20210287422Abstract: Techniques for performing ray tracing for a ray are provided. The techniques include, based on first traversal of a bounding volume hierarchy, identifying a first memory page that is classified as resident, obtaining a first portion of the bounding volume hierarchy associated with the first memory page, traversing the first portion of the bounding volume hierarchy according to a ray intersection test, based on second traversal of the bounding volume hierarchy, identifying a second memory page that is classified as valid and non-resident, and in response to the second memory page being classified as valid and non-resident, determining that a miss occurs for each node of the bounding volume hierarchy within the second memory page.Type: ApplicationFiled: March 13, 2020Publication date: September 16, 2021Applicant: Advanced Micro Devices, Inc.Inventors: Skyler Jonathon Saleh, Fataneh Ghodrat
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Publication number: 20210065758Abstract: A technique for processing computer instructions is provided. The technique includes obtaining information for an instruction state memory entry for an instruction; identifying, for the instruction state memory entry, a slot in an instruction state memory having selectably powered rows and blocks, based on clustering criteria; and placing the instruction state memory entry into the identified slot.Type: ApplicationFiled: August 29, 2019Publication date: March 4, 2021Applicant: Advanced Micro Devices, Inc.Inventors: Fataneh Ghodrat, Tien E. Wei
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Patent number: 10198789Abstract: Techniques for allowing cache access returns out of order are disclosed. A return ordering queue exists for each of several cache access types and stores outstanding cache accesses in the order in which those accesses were made. When a cache access request for a particular type is at the head of the return ordering queue for that type and the cache access is available for return to the wavefront that made that access, the cache system returns the cache access to the wavefront. Thus, cache accesses can be returned out of order with respect to cache accesses of different types. Allowing out-of-order returns can help to improve latency, for example in the situation where a relatively low-latency access type (e.g., a read) is issued after a relatively high-latency access type (e.g., a texture sampler operation).Type: GrantFiled: December 13, 2016Date of Patent: February 5, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Daniel Schneider, Fataneh Ghodrat
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Publication number: 20180165790Abstract: Techniques for allowing cache access returns out of order are disclosed. A return ordering queue exists for each of several cache access types and stores outstanding cache accesses in the order in which those accesses were made. When a cache access request for a particular type is at the head of the return ordering queue for that type and the cache access is available for return to the wavefront that made that access, the cache system returns the cache access to the wavefront. Thus, cache accesses can be returned out of order with respect to cache accesses of different types. Allowing out-of-order returns can help to improve latency, for example in the situation where a relatively low-latency access type (e.g., a read) is issued after a relatively high-latency access type (e.g., a texture sampler operation).Type: ApplicationFiled: December 13, 2016Publication date: June 14, 2018Applicant: Advanced Micro Devices, Inc.Inventors: Daniel Schneider, Fataneh Ghodrat