Patents by Inventor Federico Giovanni Ziglioli

Federico Giovanni Ziglioli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10794783
    Abstract: A pressure sensing device may include a body configured to distribute a load applied between first and second parts positioned one against the other, and a pressure sensor carried by the body. The pressure sensor may include a support body, and an IC die mounted with the support body and defining a cavity. The IC die may include pressure sensing circuitry responsive to bending associated with the cavity, and an IC interface coupled to the pressure sensing circuitry.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: October 6, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alberto Pagani, Federico Giovanni Ziglioli, Bruno Murari
  • Patent number: 10770432
    Abstract: A die structure includes a first die having a first surface and a second surface opposite the first surface. The first die includes sidewalls extending between the first and second surfaces. The die structure includes conductive ink printed traces including a first group of the conductive ink printed traces on the first surface of the first semiconductor die. A second group of the conductive ink printed traces are on the second surface of the semiconductor die, and a third group of the conductive ink printed traces are on the sidewalls of the semiconductor die.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: September 8, 2020
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10756005
    Abstract: A semiconductor device including one or more semiconductor dice, a lead frame including an array of signal-carrying leads electrically coupled with the semiconductor die, and a power supply connection for the at least one semiconductor die arranged centrally thereof.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: August 25, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10707153
    Abstract: A semiconductor device includes: one or more semiconductor dice, a die pad supporting the semiconductor die or dice, a package molded onto the semiconductor die or dice supported by said die pad, wherein the die pad is exposed at the surface of the package, and the exposed die pad with an etched pattern therein to form at least one electrical contact land in the die pad.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 7, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Publication number: 20200203264
    Abstract: A semiconductor chip is mounted on a leadframe. A first portion of an insulating package for the semiconductor chip is formed from laser direct structuring (LDS) material molded onto the semiconductor chip. A conductive formation (provided by laser-drilling the LDS material and plating) extends between the outer surface of the first portion of insulating package and the semiconductor chip. An electrically conductive clip is applied onto the outer surface of the first portion of the insulating package, with the electrically conductive clip electrically coupled to the conductive formation and the leadframe. A second portion of the insulating package is made from package molding material (epoxy compound) molded onto the electrically conductive clip and applied onto the outer surface of the first portion of the insulating package.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 25, 2020
    Applicant: STMicroelectronics S.r.l.
    Inventor: Federico Giovanni ZIGLIOLI
  • Patent number: 10598578
    Abstract: A tensile stress measurement device is to be attached to an object to be measured. The tensile stress measurement device may include an IC having a semiconductor substrate and tensile stress detection circuitry, the semiconductor substrate having opposing first and second attachment areas. The tensile stress measurement device may include a first attachment plate coupled to the first attachment area and extending outwardly to be attached to the object to be measured, and a second attachment plate coupled to the second attachment area and extending outwardly to be attached to the object to be measured. The tensile stress detection circuitry may be configured to detect a tensile stress imparted on the first and second attachment plates when attached to the object to be measured.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: March 24, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Alberto Pagani, Bruno Murari, Federico Giovanni Ziglioli
  • Patent number: 10529653
    Abstract: An electronic component includes one or more circuits having electrical connections coupled therewith. The electrical connections include a lead frame as well as electrical wires coupling the circuit or circuits to respective portions of the lead frame. The electrical wires may be formed as one piece with the respective portion of the lead frame without joints therebetween, e.g., by 3D printing.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: January 7, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Publication number: 20190378774
    Abstract: An assembly is provided including one or more semiconductor dice attached on a substrate, the semiconductor die provided with electrically-conductive stud bumps opposite the substrate. The stud bumps embedded in a molding compound molded thereon are exposed to grinding thus leveling the molding compound to expose the distal ends of the stud bumps at a surface of the molding compound. Recessed electrically-conductive lines extending over said surface of the molding compound with electrically-conductive lands over the distal ends of the stud bumps. A further molding compound is provided to cover the recessed electrically-conductive lines and surrounding the electrically-conductive lands.
    Type: Application
    Filed: August 26, 2019
    Publication date: December 12, 2019
    Inventor: Federico Giovanni ZIGLIOLI
  • Patent number: 10504806
    Abstract: One or more embodiments are directed to semiconductor packages that include conductive test pads that are electrically coupled to, but distinct from, the leads of the package. In one embodiment the test pads are located on the plastic packaging material, such as encapsulation material, of the package and are electrically coupled to the leads of the package by traces. The traces may also be located on the packaging material and portions of the leads. In one embodiment, all of the test pads are located on a single surface of the packaging material of the package, which may allow for ease of electrical testing of the package.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: December 10, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10497655
    Abstract: A packaged semiconductor device includes an insulating material forming a side surface of the packaged semiconductor device. An integrated-circuit chip is embedded in the insulating material and includes a communication circuit. A wiring system is embedded in the insulating material and electrically couples the integrated-circuit chip with a plurality of package contact elements. A first communication pad is formed in the side surface and is operatively coupled to the communication circuit to enable signal exchange through the first communication pad.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: December 3, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Federico Giovanni Ziglioli, Alberto Pagani
  • Patent number: 10483238
    Abstract: An integrated circuit package with improved reliability and methods for creating the same are disclosed. More specifically, integrated circuit packages are created using one or more sacrificial layers that provide support for ink printed wires prior to package processing, but are removed during package processing. Once each of the sacrificial layers is removed, molding compound is placed around each ink printed wire, which may have a substantially rectangular cross section that can vary in dimension along a length of a given wire. While substantially surrounding each wire in and of itself improves reliability, removing non-conductive paste, fillets, or other adhesive materials also minimizes adhesion issues between the molding compound and those materials, which increases the bond of the molding compound to the package and its components. The net result is a more reliable integrated circuit package that is less susceptible to internal cracking and wire damage.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: November 19, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10468344
    Abstract: A method of manufacturing semiconductor products includes: providing a semiconductor product lead frame including a semiconductor die mounting area and an array of electrically conductive leads, molding semiconductor product package molding material, e.g., laser direct structuring material, and forming on the package molding material molded onto the lead frame electrically-conductive lines extending between the semiconductor die mounting area and the array of electrically-conductive leads.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: November 5, 2019
    Assignee: STMicroelectronics S.r.L.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10455692
    Abstract: A packaged device has a die of semiconductor material bonded to a support. An electromagnetic shielding structure surrounds the die and is formed by a grid structure of conductive material extending into the support and an electromagnetic shield, coupled together. A packaging mass embeds both the die and the electromagnetic shield. The electromagnetic shield is formed by a plurality of metal ribbon sections overlying the die and embedded in the packaging mass. Each metal ribbon section has a thickness-to-width ratio between approximately 1:2 and approximately 1:50.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: October 22, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Federico Giovanni Ziglioli
  • Patent number: 10424525
    Abstract: An assembly is provided including one or more semiconductor dice attached on a substrate, the semiconductor die provided with electrically-conductive stud bumps opposite the substrate. The stud bumps embedded in a molding compound molded thereon are exposed to grinding thus leveling the molding compound to expose the distal ends of the stud bumps at a surface of the molding compound. Recessed electrically-conductive lines extending over said surface of the molding compound with electrically-conductive lands over the distal ends of the stud bumps. A further molding compound is provided to cover the recessed electrically-conductive lines and surrounding the electrically-conductive lands.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: September 24, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Federico Giovanni Ziglioli
  • Publication number: 20190287944
    Abstract: A die structure includes a first die having a first surface and a second surface opposite the first surface. The first die includes sidewalls extending between the first and second surfaces. The die structure includes conductive ink printed traces including a first group of the conductive ink printed traces on the first surface of the first semiconductor die. A second group of the conductive ink printed traces are on the second surface of the semiconductor die, and a third group of the conductive ink printed traces are on the sidewalls of the semiconductor die.
    Type: Application
    Filed: March 13, 2018
    Publication date: September 19, 2019
    Inventor: Federico Giovanni Ziglioli
  • Publication number: 20190259629
    Abstract: A method, comprises: providing a laminar support member, having a front surface, with at least one semiconductor die mounting location lying in a plane thereon, arranging at the at least one semiconductor die mounting location at least one semiconductor die having a front surface and a back surface, with the back surface thereof towards the front surface of the support member and with the front surface thereof having die pads, arranging at the front surface of the support member sidewise of the at least one semiconductor die mounting location a plurality of electrically-conductive bodies, the electrically-conductive bodies arranged at respective recesses in the support member, wherein the electrically-conductive bodies protrude from the plane away from the front surface of the support member, providing a filling of molding material over the laminar support member between the at least one semiconductor die and the electrically-conductive bodies, and providing electrically-conductive lines between selected ones
    Type: Application
    Filed: February 12, 2019
    Publication date: August 22, 2019
    Inventor: Federico Giovanni Ziglioli
  • Publication number: 20190181076
    Abstract: A method of producing leadframes for semiconductor devices comprises: providing a plurality of electrically-conductive plates, forming in the electrically conductive plates homologous passageway patterns according to a desired semiconductor device leadframe pattern, joining together the plurality of plates with the homologous passageway patterns formed therein mutually in register by producing a multilayered leadframe exhibiting the desired leadframe pattern and a thickness which is the sum of the thicknesses of the plates in the plurality of electrically-conductive plates.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 13, 2019
    Inventors: Dario VITELLO, Fabio MARCHISI, Alberto ARRIGONI, Federico FREGO, Federico Giovanni ZIGLIOLI, Paolo CREMA
  • Publication number: 20190172782
    Abstract: A substrate for mounting a semiconductor device includes an insulating layer having first and second opposed surfaces defining a thickness. First and second electrically conductive lands are included in the insulating layer. The first electrically conductive lands extend through the whole thickness of the insulating layer and are exposed on both the first and second opposed surfaces. The second electrically conductive lands have a thickness less than the thickness of the insulating layer and are exposed only at the first surface. Electrically conductive lines at the first surface of the insulating layer couple certain ones of the first electrically conductive lands with certain ones of the second electrically conductive lands. The semiconductor device is mounted to the first surface of the insulating layer. Wire bonding may be used to electrically coupling the semiconductor device to certain ones of the first and second lands.
    Type: Application
    Filed: February 6, 2019
    Publication date: June 6, 2019
    Applicant: STMicroelectronics S.r.l.
    Inventor: Federico Giovanni ZIGLIOLI
  • Patent number: 10294096
    Abstract: In order to manufacture a packaged device, a die having a sensitive region is bonded to a support, and a packaging mass of moldable material is molded on the support so as to surround the die. During molding of the packaging mass, a chamber is formed, which faces the sensitive region and is connected to the outside environment. To this end, a sacrificial mass of material that may evaporate/sublimate is dispensed on the sensitive region; the packaging mass is molded on the sacrificial mass; a through hole is formed in the packaging mass to extend as far as the sacrificial mass; the sacrificial mass is evaporated/sublimated through the hole.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: May 21, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Federico Giovanni Ziglioli
  • Publication number: 20190115287
    Abstract: A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate.
    Type: Application
    Filed: October 4, 2018
    Publication date: April 18, 2019
    Inventors: Michele DERAI, Federico Giovanni ZIGLIOLI