Patents by Inventor Fei-Yuh Chen
Fei-Yuh Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9601585Abstract: A transistor includes an isolation region surrounding an active region. The transistor also includes a gate dielectric layer over a portion of the active region. The transistor further includes a gate electrode over the gate dielectric layer. The portion of the active region under the gate dielectric layer includes a channel region between a drain region and a source region, and at least one wing region adjoining the channel region. The at least one wing region has a base edge adjoining the channel region. The at least one wing region is polygonal or curved.Type: GrantFiled: June 26, 2015Date of Patent: March 21, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Liang Chu, Fei-Yuh Chen, Yi-Sheng Chen, Shih-Kuang Hsiao, Chun Lin Tsai, Kong-Beng Thei
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Patent number: 9299806Abstract: An integrated circuit and a method of forming is provided. The method includes forming a first well in a substrate, the first well having a first conductivity type, and forming a first source/drain region in the first well, the first source/drain region having a second conductivity type. A resistance protection ring is formed on the substrate.Type: GrantFiled: May 18, 2015Date of Patent: March 29, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Sheng Chen, Chen-Liang Chu, Shih-Kuang Hsiao, Fei-Yuh Chen, Kong-Beng Thei
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Publication number: 20150295055Abstract: A transistor includes an isolation region surrounding an active region. The transistor also includes a gate dielectric layer over a portion of the active region. The transistor further includes a gate electrode over the gate dielectric layer. The portion of the active region under the gate dielectric layer includes a channel region between a drain region and a source region, and at least one wing region adjoining the channel region. The at least one wing region has a base edge adjoining the channel region. The at least one wing region is polygonal or curved.Type: ApplicationFiled: June 26, 2015Publication date: October 15, 2015Inventors: Chen-Liang CHU, Fei-Yuh CHEN, Yi-Sheng CHEN, Shih-Kuang HSIAO, Chun Lin TSAI, Kong-Beng THEI
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Publication number: 20150249144Abstract: An integrated circuit and a method of forming is provided. The method includes forming a first well in a substrate, the first well having a first conductivity type, and forming a first source/drain region in the first well, the first source/drain region having a second conductivity type. A resistance protection ring is formed on the substrate.Type: ApplicationFiled: May 18, 2015Publication date: September 3, 2015Inventors: Yi-Sheng Chen, Chen-Liang Chu, Shih-Kuang Hsiao, Fei-Yuh Chen, Kong-Beng Thei
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Patent number: 9099556Abstract: A semiconductor device includes an active region having a channel region and at least a wing region adjoining the channel region under the gate dielectric layer. The at least one wing region may be two symmetrical wing regions across the channel region.Type: GrantFiled: August 19, 2011Date of Patent: August 4, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Liang Chu, Fei-Yuh Chen, Yi-Sheng Chen, Shih-Kuang Hsiao, Chun Lin Tsai, Kong-Beng Thei
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Patent number: 9070663Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.Type: GrantFiled: August 16, 2013Date of Patent: June 30, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Liang Chu, Fei-Yuh Chen, Chih-Wen Yao
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Patent number: 8673712Abstract: Presented herein is a field effect transistor device, optionally a lateral power transistor, and a method for forming the same, comprising providing a substrate, creating a doped buried layer, and creating a primary well in the substrate on the buried layer. A drift drain may be created in the primary well and a counter implant region implanted in the primary well and between the drift drain and the buried layer. The primary well may comprise a first and second implant region with the second implant region at a depth less than the first. The counter implant may be at a depth between the first and second implant regions. The primary well and counter implant region may comprise dopants of the same conductivity type, or both p+-type dopants. A gate may be formed over a portion of a drift drain.Type: GrantFiled: July 20, 2012Date of Patent: March 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Kuang Hsiao, Chen-Liang Chu, Yi-Sheng Chen, Fei-Yuh Chen, Kong-Beng Thei
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Publication number: 20130337644Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.Type: ApplicationFiled: August 16, 2013Publication date: December 19, 2013Inventors: Chen-Liang Chu, Fei-Yuh Chen, Chih-Wen Yao
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Patent number: 8513712Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.Type: GrantFiled: September 28, 2009Date of Patent: August 20, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Liang Chu, Fei-Yuh Chen, Chih-Wen Yao
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Publication number: 20130043533Abstract: A semiconductor device includes an active region having a channel region and at least a wing region adjoining the channel region under the gate dielectric layer. The at least one wing region may be two symmetrical wing regions across the channel region.Type: ApplicationFiled: August 19, 2011Publication date: February 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Liang CHU, Fei-Yuh CHEN, Yi-Sheng CHEN, Shih-Kuang HSIAO, Chun Lin TSAI, Kong-Beng THEI
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Patent number: 8377787Abstract: A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the semiconductor substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.Type: GrantFiled: June 8, 2011Date of Patent: February 19, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Liang Chu, Chun-Ting Liao, Fei-Yuh Chen, Tsung-Yi Huang
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Patent number: 8183626Abstract: An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.Type: GrantFiled: February 14, 2011Date of Patent: May 22, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Liang Chu, Chun-Ting Liao, Tsung-Yi Huang, Fei-Yuh Chen
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Publication number: 20110237041Abstract: A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the semiconductor substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.Type: ApplicationFiled: June 8, 2011Publication date: September 29, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Liang Chu, Chun-Ting Liao, Fei-Yuh Chen, Tsung-Yi Huang
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Patent number: 7977743Abstract: A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.Type: GrantFiled: February 25, 2009Date of Patent: July 12, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Liang Chu, Chun-Ting Liao, Fei-Yuh Chen, Tsung-Yi Huang
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Publication number: 20110163375Abstract: An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.Type: ApplicationFiled: February 14, 2011Publication date: July 7, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Liang Chu, Chun-Ting Liao, Tsung-Yi Huang, Fei-Yuh Chen
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Publication number: 20110073962Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.Type: ApplicationFiled: September 28, 2009Publication date: March 31, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Liang Chu, Fei-Yuh Chen, Chih-Wen Yao
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Patent number: 7888734Abstract: An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.Type: GrantFiled: December 4, 2008Date of Patent: February 15, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Liang Chu, Chun-Ting Liao, Tsung-Yi Huang, Fei-Yuh Chen
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Publication number: 20100213542Abstract: A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.Type: ApplicationFiled: February 25, 2009Publication date: August 26, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Liang Chu, Chun-Ting Liao, Fei-Yuh Chen, Tsung-Yi Huang
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Publication number: 20100140687Abstract: An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.Type: ApplicationFiled: December 4, 2008Publication date: June 10, 2010Inventors: Chen-Liang Chu, Chun-Ting Liao, Tsung-Yi Huang, Fei-Yuh Chen
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Patent number: 7205176Abstract: An MEMS mirror structure is formed using an etching process that forms sidewall oxide spacers while maintaining the integrity of the oxide layer formed over the reflective layer of the MEMS mirror structure. The discrete mirror structure is formed to include a reflective layer sandwiched between oxide layers and with a protect layer formed over the upper oxide layer. A spacer oxide layer is formed to cover the structure and oxide spacers are formed on sidewalls of the discrete structure using a selective etch process that is terminated when horizontal portions of the spacer oxide layer have cleared to expose the release layer formed below the discrete mirror structure and the protect layer. The superjacent protect layer prevents the spacer oxide etch process from attacking the upper oxide layer and therefore maintains the integrity of the upper oxide layer and the functionality of the mirror structure.Type: GrantFiled: October 29, 2004Date of Patent: April 17, 2007Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Fei-Yuh Chen, Wei-Ya Wang, Yuh-Hwa Chang, Tzu-Yang Wu