Patents by Inventor Fei-Yun Chen
Fei-Yun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967667Abstract: A micro light-emitting diode structure is provided. The micro light-emitting diode structure includes an epitaxial layer. The micro light-emitting diode structure also includes a reflecting layer disposed on the epitaxial layer. The micro light-emitting diode structure further includes a patterned electrode layer disposed between the epitaxial layer and the reflecting layer. The patterned electrode layer is divided into a plurality of patterned electrode segments, and the patterned electrode segments are separated from each other. Moreover, the micro light-emitting diode structure includes a first-type electrode and a second-type electrode disposed on the reflecting layer and electrically connected to the epitaxial layer.Type: GrantFiled: October 14, 2021Date of Patent: April 23, 2024Assignee: PLAYNITRIDE DISPLAY CO., LTD.Inventors: Chee-Yun Low, Fei-Hong Chen, Pai-Yang Tsai
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Publication number: 20240113187Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.Type: ApplicationFiled: January 5, 2023Publication date: April 4, 2024Inventors: Jhu-Min Song, Ying-Chou Chen, Yi-Kai Ciou, Chien-Chih Chou, Fei-Yun Chen, Yu-Chang Jong, Chi-Te Lin
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Publication number: 20240097051Abstract: A Schottky diode includes a substrate, a first drift region in the substrate, a second drift region in the substrate, a first dielectric layer disposed over the substrate, a first doped region in the first drift region, a second doped region in the second drift region, a third doped region in the first drift region, and a metal field plate disposed over the first dielectric layer. The first drift region and the first doped region include a first conductivity type. The second drift region, the second doped region and third doped region include a second conductivity type complementary to the first conductivity type. The first dielectric layer overlaps a portion of the first drift region and a portion of the second drift region. The second doped region is separated from the first doped region.Type: ApplicationFiled: January 16, 2023Publication date: March 21, 2024Inventors: GUAN-YI LI, CHIA-CHENG HO, CHAN-YU HUNG, FEI-YUN CHEN
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Publication number: 20240071833Abstract: The present disclosure relates to a semiconductor device with a hybrid fin-dielectric region. The semiconductor device includes a substrate, a source region and a drain region laterally separated by a hybrid fin-dielectric (HFD) region. A gate electrode is disposed above the HFD region and the HFD region includes a plurality of fins covered by a dielectric and separated from the source region and the drain region by the dielectric.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Inventors: Yi-Huan Chen, Huan-Chih Yuan, Yu-Chang Jong, Scott Yeh, Fei-Yun Chen, Yi-Hao Chen, Ting-Wei Chou
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Publication number: 20240072210Abstract: A micro light emitting diode structure including an epitaxial structure, a first insulating layer and a second insulating layer is provided. The epitaxial structure includes a first type semiconductor layer, a light emitting layer and a second type semiconductor layer. The first type semiconductor layer, the light emitting layer and a first portion of the second type semiconductor layer form a mesa. A second portion of the second type semiconductor layer is recessed relative the mesa to form a mesa surface. The first insulating layer covers from a top surface of the mesa to the mesa surface along a first side surface of the mesa, and exposes the second side surface. The second insulating layer directly covers a second side surface of the second portion, wherein a thickness ratio of the first insulating layer to the second insulating layer is between 10 and 50.Type: ApplicationFiled: October 21, 2022Publication date: February 29, 2024Applicant: PlayNitride Display Co., Ltd.Inventors: Chee-Yun Low, Yun-Syuan Chou, Hung-Hsuan Wang, Pai-Yang Tsai, Fei-Hong Chen, Tzu-Yang Lin
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Publication number: 20240047542Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a source region, a drain region, a gate region and a gate oxide. The gate region is disposed between the source region and the drain region. The gate oxide is disposed on the gate region. A bottom interface is between the gate region and the gate oxide, and an entire of the bottom interface is substantially flat.Type: ApplicationFiled: August 3, 2022Publication date: February 8, 2024Inventors: JHIH-BIN CHEN, HUNG-SHU HUANG, JHU-MIN SONG, CHIEN-CHIH CHOU, YU-CHANG JONG, FEI-YUN CHEN
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Publication number: 20240030292Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a deep trench isolation (DTI), an interconnect structure, and a conductive pillar. The DTI is disposed in the substrate and the interconnect structure is disposed over the substrate. The conductive pillar extends from the interconnect structure toward the substrate and penetrates the DTI. A method of manufacturing the semiconductor structure is also provided.Type: ApplicationFiled: July 20, 2022Publication date: January 25, 2024Inventors: CHIA-CHENG HO, CHIA-YU WEI, CHAN-YU HUNG, FEI-YUN CHEN, YU-CHANG JONG
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Publication number: 20230378324Abstract: The present disclosure describes a structure with a conductive plate and a method for forming the structure. The structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. The structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. The structure further includes a second insulating layer in contact with the conductive plate.Type: ApplicationFiled: May 18, 2022Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chan-Yu Hung, Chia-Cheng Ho, Fei-Yun Chen, Yu-Chang Jong, Puo-Yu Chiang, Tun-Yi Ho
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Publication number: 20200215153Abstract: This disclosure provides for a method of treating and/or preventing cancer in a subject by targeting the BIK degradation pathway in combination with the administration of an active BIKDD. Also described herein are compositions comprising an active BIKDD and methods of their making an use for the treatment of cancer.Type: ApplicationFiled: December 12, 2019Publication date: July 9, 2020Inventors: Ruey-Hwa CHEN, Fei-Yun CHEN, Min-Yu HUANG
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Patent number: 9466681Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.Type: GrantFiled: June 12, 2015Date of Patent: October 11, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Liang Chu, Fei-Yun Chen, Chih-Wen Albert Yao
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Publication number: 20150279951Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.Type: ApplicationFiled: June 12, 2015Publication date: October 1, 2015Inventors: Chen-Liang Chu, Fei-Yun Chen, Chih-Wen Yao
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Patent number: 9035380Abstract: An integrated circuit includes a high-voltage well having a first doping type, a first doped region and a second doped region embedded in the high-voltage well, the first and second doped regions having a second doping type and spaced apart by a channel in the high-voltage well, source/drain regions formed in the first doped region and in the second doped region, each of the source/drain regions having the second doping type and more heavily doped than the first and second doped regions, first isolation regions spaced apart from each of the source/drain regions, and resistance protection oxide forming a ring surrounding each of the source/drain regions.Type: GrantFiled: November 27, 2012Date of Patent: May 19, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Sheng Chen, Chen-Liang Chu, Shih-Kuang Hsiao, Fei-Yun Chen, Kong-Beng Thei
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Publication number: 20140145261Abstract: An integrated circuit includes a high-voltage well having a first doping type, a first doped region and a second doped region embedded in the high-voltage well, the first and second doped regions having a second doping type and spaced apart by a channel in the high-voltage well, source/drain regions formed in the first doped region and in the second doped region, each of the source/drain regions having the second doping type and more heavily doped than the first and second doped regions, first isolation regions spaced apart from each of the source/drain regions, and resistance protection oxide forming a ring surrounding each of the source/drain regions.Type: ApplicationFiled: November 27, 2012Publication date: May 29, 2014Applicant: Taiwan Semiconductor Manufacturing CompanyInventors: Yi-Sheng Chen, Chen-Liang Chu, Shih-Kuang Hsiao, Fei-Yun Chen, Kong-Beng Thei
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Patent number: 8691100Abstract: A method comprising providing a first substrate and forming a first sacrificial layer over the first substrate, the first sacrificial layer comprising a curved surface portion, and forming a curved micromirror by depositing a reflective material over at the curved surface portion.Type: GrantFiled: June 9, 2006Date of Patent: April 8, 2014Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Dah-Chuen Ho, Eugene Chu, Yuh-Haw Chang, Fei-Yun Chen, Michael Wu, Eric Chao
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Publication number: 20140021539Abstract: Presented herein is a field effect transistor device, optionally a lateral power transistor, and a method for forming the same, comprising providing a substrate, creating a doped buried layer, and creating a primary well in the substrate on the buried layer. A drift drain may be created in the primary well and a counter implant region implanted in the primary well and between the drift drain and the buried layer. The primary well may comprise a first and second implant region with the second implant region at a depth less than the first. The counter implant may be at a depth between the first and second implant regions. The primary well and counter implant region may comprise dopants of the same conductivity type, or both p+-type dopants. A gate may be formed over a portion of a drift drain.Type: ApplicationFiled: July 20, 2012Publication date: January 23, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Kuang Hsiao, Chen-Liang Chu, Yi-Sheng Chen, Fei-Yun Chen, Kong-Beng Thei
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Patent number: 7576374Abstract: A new method is provided to create a polysilicon fuse. The invention provides for applying a first oxide plasma treatment to the surface of the created polysilicon fuse, creating a thin layer of native oxide over the surface of the created polysilicon fuse, followed by a DI water rinse. This thin layer of native oxide is made more robust by applying a second oxide plasma treatment to exposed surfaces, this more robust layer of native oxide protects the polysilicon fuse during subsequent processing steps of wet photoresist and polymer removal.Type: GrantFiled: June 26, 2006Date of Patent: August 18, 2009Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yuan-Pang Lee, Chen-Shiang Shieh, Ping-Hung Yin, Fei-Yun Chen, Yuan-Ko Hwang
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Patent number: 7384799Abstract: A method for forming a MEMS device using an amorphous silicon layer as a release layer includes etching superjacent films and using the amorphous silicon layer as an etch stop layer. The amorphous silicon layer is resistant to attack during the post-etch solvent stripping operation due to the oxidation of exposed portions of the amorphous silicon layer by use of an oxygen plasma.Type: GrantFiled: January 26, 2005Date of Patent: June 10, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fei-Yun Chen, Ni-Hwi Kuan, Yuh-Hwa Chang, Yuan-Pang Lee, Yuan-Ko Hwang, Shuh-Shun Chen
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Publication number: 20070285760Abstract: A method comprising providing a first substrate and forming a first sacrificial layer over the first substrate, the first sacrificial layer comprising a curved surface portion, and forming a curved micromirror by depositing a reflective material over at the curved surface portion.Type: ApplicationFiled: June 9, 2006Publication date: December 13, 2007Inventors: Dah-Chuen Ho, Eugene Chu, Yuh-Haw Chang, Fei-Yun Chen, Michael Wu, Eric Chao
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Patent number: 7294279Abstract: A method for releasing a micromechanical structure. A substrate is provided. At least one micromechanical structural layer is provided above the substrate, wherein the micromechanical structural layer is sustained by a sacrificial layer of a silicon material. An amine-based etchant is provided to etch the silicon material. That is, during performing a post-cleaning procedure with an amine-based etchant, polymer residue and the sacrificial layer of silicon can be simultaneously removed without any additional etching processes.Type: GrantFiled: March 17, 2005Date of Patent: November 13, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fei-Yun Chen, Tzu-Yang Wu, Shih-Shiung Chen
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Patent number: 7192489Abstract: A method for removing polymer containing residues from a semiconductor wafer including metal containing features including providing a semiconductor wafer having a process surface including metal containing features said process surface at least partially covered with polymer containing residues; and, subjecting the semiconductor wafer to a series of cleaning steps including sequentially exposing the process surface to at least one primary solvent and at least one intermediate solvent the at least one intermediate solvent comprising an ammonium nitrate containing solution.Type: GrantFiled: May 1, 2003Date of Patent: March 20, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Hsin Lo, Fei-Yun Chen