Patents by Inventor Felipe Ricardo Clayton
Felipe Ricardo Clayton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11979151Abstract: An integrated circuit includes a plurality of analog inputs, and an analog multiplexer (MUX). The MUX includes a common output node configured to provide a MUX output, a plurality of analog switches, and a shared buffer. Each switch includes a corresponding bootstrap circuit coupled to a control electrode of a corresponding pass transistor in which the corresponding bootstrap circuit includes a corresponding boosting capacitor. Each analog switch of the plurality of analog switches has a first input coupled to a corresponding analog input of the plurality of analog inputs, a second input, and an output coupled to the common output node. The shared buffer has an input coupled to the common output node and coupled to provide a common buffered MUX output to the second input of each of the plurality of analog switches.Type: GrantFiled: September 20, 2022Date of Patent: May 7, 2024Assignee: NXP USA, Inc.Inventors: Khoi Mai, Michael Todd Berens, Andre Luis Vilas Boas, Felipe Ricardo Clayton
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Publication number: 20240097686Abstract: An integrated circuit includes a plurality of analog inputs, and an analog multiplexer (MUX). The MUX includes a common output node configured to provide a MUX output, a plurality of analog switches, and a shared buffer. Each switch includes a corresponding bootstrap circuit coupled to a control electrode of a corresponding pass transistor in which the corresponding bootstrap circuit includes a corresponding boosting capacitor. Each analog switch of the plurality of analog switches has a first input coupled to a corresponding analog input of the plurality of analog inputs, a second input, and an output coupled to the common output node. The shared buffer has an input coupled to the common output node and coupled to provide a common buffered MUX output to the second input of each of the plurality of analog switches.Type: ApplicationFiled: September 20, 2022Publication date: March 21, 2024Inventors: Khoi Mai, Michael Todd Berens, Andre Luis Vilas Boas, Felipe Ricardo Clayton
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Patent number: 11808804Abstract: An integrated circuit (IC) includes subcircuits, power switches coupled to pass load current to a respective one of the subcircuits when activated by a respective switch control signal, and sensing circuits. Each of the sensing circuits is coupled to a respective one of the subcircuits, wherein the sensing circuits are configured to generate sense currents that are proportional to the respective load currents. The IC also includes a conversion circuit configured to receive at least one of the sense currents and to convert the at least one of the sense currents to an equivalent multi-bit digital signal, a timestamp circuit configured to generate a timestamp value that is correlated with the multi-bit digital signal, and a controller configured to provide signals to operate the power switches and the sensing circuits.Type: GrantFiled: December 15, 2020Date of Patent: November 7, 2023Assignee: NXP USA, Inc.Inventors: Antonio Mauricio Brochi, Felipe Ricardo Clayton
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Patent number: 11733277Abstract: An integrated circuit includes an analog-to-digital converter (ADC) configured to receive input voltage, and first and second reference voltages, and outputs digital code representing ratios between the input voltage and the first and the second reference voltages. The first and second reference voltages are generated by a reference generator using different current densities. During a first stage, the ADC samples the first input voltage and the first reference voltage and transfers equivalent charge of the sampled first input voltage and first reference voltage to an integration capacitor. During a second stage, the ADC samples the second reference voltage and transfers equivalent charge of the sampled second reference voltage to the integration capacitor. The ADC provides one bit of digital code based on total charge stored on the integration capacitor after the transfers of charge of the sampled input voltage, and the sampled first and second reference voltages.Type: GrantFiled: December 7, 2021Date of Patent: August 22, 2023Assignee: NXP B.V.Inventors: Ricardo Pureza Coimbra, Edevaldo Pereira da Silva, Jr., Felipe Ricardo Clayton
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Publication number: 20230176097Abstract: An integrated circuit includes an analog-to-digital converter (ADC) configured to receive input voltage, and first and second reference voltages, and outputs digital code representing ratios between the input voltage and the first and the second reference voltages. The first and second reference voltages are generated by a reference generator using different current densities. During a first stage, the ADC samples the first input voltage and the first reference voltage and transfers equivalent charge of the sampled first input voltage and first reference voltage to an integration capacitor. During a second stage, the ADC samples the second reference voltage and transfers equivalent charge of the sampled second reference voltage to the integration capacitor. The ADC provides one bit of digital code based on total charge stored on the integration capacitor after the transfers of charge of the sampled input voltage, and the sampled first and second reference voltages.Type: ApplicationFiled: December 7, 2021Publication date: June 8, 2023Inventors: Ricardo Pureza Coimbra, Edevaldo Pereira da Silva, JR., Felipe Ricardo Clayton
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Patent number: 11422168Abstract: An on-chip low-voltage current sensing circuit for measuring current in an integrated circuit (IC). In one embodiment, an IC formed on a substrate, which includes a plurality of subcircuits, and a plurality of sensing circuits coupled to the plurality of subcircuits, respectively. The plurality of sensing circuits are configured to generate a plurality of currents, respectively, that are proportional to a plurality of load currents, respectively, consumed by the plurality of subcircuits, respectively, during operation thereof. A circuit is coupled to the plurality of sensing circuits and configured to generate a signal based on an aggregate of the plurality of currents.Type: GrantFiled: September 16, 2020Date of Patent: August 23, 2022Assignee: NXP USA, Inc.Inventor: Felipe Ricardo Clayton
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Publication number: 20220187358Abstract: An integrated circuit (IC) includes subcircuits, power switches coupled to pass load current to a respective one of the subcircuits when activated by a respective switch control signal, and sensing circuits. Each of the sensing circuits is coupled to a respective one of the subcircuits, wherein the sensing circuits are configured to generate sense currents that are proportional to the respective load currents. The IC also includes a conversion circuit configured to receive at least one of the sense currents and to convert the at least one of the sense currents to an equivalent multi-bit digital signal, a timestamp circuit configured to generate a timestamp value that is correlated with the multi-bit digital signal, and a controller configured to provide signals to operate the power switches and the sensing circuits.Type: ApplicationFiled: December 15, 2020Publication date: June 16, 2022Inventors: Antonio Mauricio Brochi, Felipe Ricardo Clayton
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Publication number: 20220082595Abstract: An on-chip low-voltage current sensing circuit for measuring current in an integrated circuit (IC). In one embodiment, an IC formed on a substrate, which includes a plurality of subcircuits, and a plurality of sensing circuits coupled to the plurality of subcircuits, respectively. The plurality of sensing circuits are configured to generate a plurality of currents, respectively, that are proportional to a plurality of load currents, respectively, consumed by the plurality of subcircuits, respectively, during operation thereof. A circuit is coupled to the plurality of sensing circuits and configured to generate a signal based on an aggregate of the plurality of currents.Type: ApplicationFiled: September 16, 2020Publication date: March 17, 2022Inventor: Felipe Ricardo Clayton
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Patent number: 10979033Abstract: A current-controlled oscillator receives an input current. Ramp voltage generating circuitry generates first and second ramp voltages in response to the input current. Selecting circuitry selects one of the first and second ramp voltages depending on their relative values. Switching circuitry receives a selected ramp voltage, generates a signal based on the selected ramp voltage relative to a reference voltage, and outputs a clock signal. In one embodiment, a comparator receives the reference voltage, one of the first and second ramp voltages, and outputs a comparison signal. Logic circuitry controls the ramp voltage generating circuitry to output one of the ramp voltages during one half of a clock cycle and to output the other ramp voltage during another half cycle of the clock signal based on the comparison signal and logic states of the logic circuitry.Type: GrantFiled: July 27, 2020Date of Patent: April 13, 2021Assignee: NXP USA, Inc.Inventors: Andre Luis Vilas Boas, Felipe Ricardo Clayton
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Publication number: 20200358428Abstract: A current-controlled oscillator receives an input current. Ramp voltage generating circuitry generates first and second ramp voltages in response to the input current. Selecting circuitry selects one of the first and second ramp voltages depending on their relative values. Switching circuitry receives a selected ramp voltage, generates a signal based on the selected ramp voltage relative to a reference voltage, and outputs a clock signal. In one embodiment, a comparator receives the reference voltage, one of the first and second ramp voltages, and outputs a comparison signal. Logic circuitry controls the ramp voltage generating circuitry to output one of the ramp voltages during one half of a clock cycle and to output the other ramp voltage during another half cycle of the clock signal based on the comparison signal and logic states of the logic circuitry.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: Andre Luis Vilas Boas, Felipe Ricardo Clayton
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Patent number: 10734975Abstract: A current-controlled oscillator receives an input current. Ramp voltage generating circuitry generates first and second ramp voltages in response to the input current. Selecting circuitry selects one of the first and second ramp voltages depending on their relative values. Switching circuitry receives a selected ramp voltage, generates a signal based on the selected ramp voltage relative to a reference voltage, and outputs a clock signal. In one embodiment, a comparator receives the reference voltage, one of the first and second ramp voltages, and outputs a comparison signal. Logic circuitry controls the ramp voltage generating circuitry to output one of the ramp voltages during one half of a clock cycle and to output the other ramp voltage during another half cycle of the clock signal based on the comparison signal and logic states of the logic circuitry.Type: GrantFiled: May 8, 2019Date of Patent: August 4, 2020Assignee: NXP USA, Inc.Inventors: Andre Luis Vilas Boas, Felipe Ricardo Clayton
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Patent number: 10394264Abstract: A back bias voltage generator circuit includes a first resistive element connected in series with a second resistive element; a first amplifier having a first input coupled to an input voltage, a second input coupled to a first node at a first terminal of the first resistive element, and an output coupled to an N-polarity metal-oxide semiconductor (NMOS) bias voltage node. A second amplifier has a first input coupled to a symmetrical voltage, a second input coupled to a second node between a second terminal of the first resistive element and a first terminal of the second resistive element, and an output coupled to a P-polarity metal-oxide semiconductor (PMOS) bias voltage node and the second terminal of the second resistive element. The symmetrical voltage is between a highest supply voltage and a lowest supply voltage coupled to the first amplifier.Type: GrantFiled: February 9, 2018Date of Patent: August 27, 2019Assignee: NXP USA, Inc.Inventors: Ricardo Pureza Coimbra, Javier Mauricio Olarte Gonzalez, Ivan Carlos Ribeiro do Nascimento, Felipe Ricardo Clayton, Stefano Pietri, Charles Eric Seaberg
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Publication number: 20190250656Abstract: A back bias voltage generator circuit includes a first resistive element connected in series with a second resistive element; a first amplifier having a first input coupled to an input voltage, a second input coupled to a first node at a first terminal of the first resistive element, and an output coupled to an N-polarity metal-oxide semiconductor (NMOS) bias voltage node. A second amplifier has a first input coupled to a symmetrical voltage, a second input coupled to a second node between a second terminal of the first resistive element and a first terminal of the second resistive element, and an output coupled to a P-polarity metal-oxide semiconductor (PMOS) bias voltage node and the second terminal of the second resistive element. The symmetrical voltage is between a highest supply voltage and a lowest supply voltage coupled to the first amplifier.Type: ApplicationFiled: February 9, 2018Publication date: August 15, 2019Inventors: Ricardo Pureza Coimbra, Javier Mauricio Olarte Gonzalez, Ivan Carlos Ribeiro do Nascimento, Felipe Ricardo Clayton, Stefano Pietri, Charles Eric Seaberg
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Patent number: 6050488Abstract: A read/write head circuit that insures the equivalence between the driving signal frequency and the resonance of the tank made up of an inductive sensor in parallel with a capacitor. The invention makes use of a voltage controlled oscillator (38)--VCO--to generate synchronism pulses (54) from the driving current generator (33), the controlling voltage being obtained from the comparison between the driving current and voltage phases through the resonant tank made up of the sensor (11) and capacitor (17) connected in parallel. The circuit further provides an amplitude limitation of the driving signal through the control of the driving current pulses applied to the inductive sensor.Type: GrantFiled: July 18, 1997Date of Patent: April 18, 2000Assignee: Telecomunicacoes Brasileiras S/A - TelebrasInventors: Felipe Ricardo Clayton, Narcizo Sabattini Junior, Antenor Capelli Junior, Manuel Augusto Miranda dos Santos Pato