Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.

Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

Abstract: A switching cell for a demultiplexer circuit includes a superconducting input signal path, at least two superconducting output signal paths, and transformers located between an intersection node and respective ends of the output signal paths. Flux applied via the transformers can influence which direction a signal propagates. The switching cell may also include power input nodes. Switching cells may be arranged in various configurations, for example a binary tree or H-tree. A superconducting inductor ladder circuit can perform a digital-to-analog conversion. Flux storage structures may be used with individual switching cells. Latching qubits may be employed. Buffer rows of switching cells may be used to reduce or eliminate cascade error.

Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.

Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.

Abstract: A switching cell for a demultiplexer circuit includes a superconducting input signal path, at least two superconducting output signal paths, and transformers located between an intersection node and respective ends of the output signal paths. Flux applied via the transformers can influence which direction a signal propagates. The switching cell may also include power input nodes. Switching cells may be arranged in various configurations, for example a binary tree or H-tree. A superconducting inductor ladder circuit can perform a digital-to-analog conversion. Flux storage structures may be used with individual switching cells. Latching qubits may be employed. Buffer rows of switching cells may be used to reduce or eliminate cascade error.

Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.