Patents by Inventor Felix P. Anderson
Felix P. Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978661Abstract: Disclosed is a structure with ultralow-K (ULK) dielectric-gap wrapped contact(s). The structure includes an opening, which extends through a dielectric layer and is aligned above a device. A contact is within the opening and electrically connected to the device. Instead of the contact completely filling the opening, a ULK dielectric-gap (e.g., an air or gas-filled gap or a void) at least partially separates the contact from the sidewall(s) of the contact opening and further wraps laterally around the contact. Also disclosed is a method for forming the structure and, particularly, for forming a ULK dielectric-gap by etching back an exposed top end of an adhesive layer initially lining a contact opening to form a gap between the sidewall(s) of the opening and the contact and then capping the gap with an additional dielectric layer such that the gap is filled with air or gas or is under vacuum.Type: GrantFiled: December 11, 2020Date of Patent: May 7, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Fuad H. Al-Amoody, Felix P. Anderson, Spencer H. Porter, Mark D. Levy, Siva P. Adusumilli
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Publication number: 20220189818Abstract: Disclosed is a structure with ultralow-K (ULK) dielectric-gap wrapped contact(s). The structure includes an opening, which extends through a dielectric layer and is aligned above a device. A contact is within the opening and electrically connected to the device. Instead of the contact completely filling the opening, a ULK dielectric-gap (e.g., an air or gas-filled gap or a void) at least partially separates the contact from the sidewall(s) of the contact opening and further wraps laterally around the contact. Also disclosed is a method for forming the structure and, particularly, for forming a ULK dielectric-gap by etching back an exposed top end of an adhesive layer initially lining a contact opening to form a gap between the sidewall(s) of the opening and the contact and then capping the gap with an additional dielectric layer such that the gap is filled with air or gas or is under vacuum.Type: ApplicationFiled: December 11, 2020Publication date: June 16, 2022Applicant: GLOBALFOUNDRIES U.S. Inc.Inventors: Fuad H. Al-Amoody, Felix P. Anderson, Spencer H. Porter, Mark D. Levy, Siva P. Adusumilli
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Patent number: 10163697Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.Type: GrantFiled: April 4, 2017Date of Patent: December 25, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Felix P. Anderson, Edward C. Cooney, III, Michael S. Dusablon, David C. Mosher
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Publication number: 20170207121Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.Type: ApplicationFiled: April 4, 2017Publication date: July 20, 2017Applicant: GlobalFoundries Inc.Inventors: Felix P. Anderson, Edward C. Cooney, III, Michael S. Dusablon, David C. Mosher
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Patent number: 9673091Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.Type: GrantFiled: June 25, 2015Date of Patent: June 6, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Felix P. Anderson, Edward C. Cooney, III, Michael S. Dusablon, David C. Mosher
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Publication number: 20160379878Abstract: Disclosed is a method of forming back end of the line (BEOL) metal levels with improved dielectric capping layer to metal wire adhesion. The method includes process step(s) designed to address dielectric capping layer to metal wire adhesion, when the metal wire(s) in a given metal level are relatively thick. These process step(s) can include, for example: (1) selective adjustment of the deposition tool used to deposit the dielectric capping layer onto metal wires based on the pattern density of the metal wires in order to ensure that those metal wires actually achieve a temperature between 360° C.-400° C.; and/or (2) deposition of a relatively thin dielectric layer on the dielectric capping layer prior to formation of the next metal level in order to reduce the tensile stress of the metal wire(s) below without causing delamination. Also disclosed is an IC chip formed using the above-described method.Type: ApplicationFiled: June 25, 2015Publication date: December 29, 2016Inventors: Felix P. Anderson, Edward C. Cooney, III, Michael S. Dusablon, David C. Mosher
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Patent number: 9284185Abstract: Integrated MEMS switches, design structures and methods of fabricating such switches are provided. The method includes forming at least one tab of sacrificial material on a side of a switching device which is embedded in the sacrificial material. The method further includes stripping the sacrificial material through at least one opening formed on the at least one tab which is on the side of the switching device, and sealing the at least one opening with a capping material.Type: GrantFiled: September 16, 2013Date of Patent: March 15, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Felix P. Anderson, Thomas L. McDevitt, Anthony K. Stamper, Julio C. Costa, Jonathan H. Hammond
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Publication number: 20150130064Abstract: Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film from edges or extreme edges (bevel) of the wafer by effectively increasing the adhesion properties of the TaN film on the wafer. The method increasing a mol percent of nitride with respect to a total tantalum plus nitride to 25% or greater during a barrier layer fabrication process.Type: ApplicationFiled: January 21, 2015Publication date: May 14, 2015Inventors: Felix P. ANDERSON, Steven P. BARKYOUMB, Edward C. COONEY, III, Thomas L. MCDEVITT, William J. MURPHY, David C. STRIPPE
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Patent number: 8969195Abstract: Processes for improving adhesion of films to semiconductor wafers and a semiconductor structure are provided. By implementing the processes of the invention, it is possible to significantly suppress defect creation, e.g., decrease particle generation, during wafer fabrication processes. More specifically, the processes described significantly reduce flaking of a TaN film from edges or extreme edges (bevel) of the wafer by effectively increasing the adhesion properties of the TaN film on the wafer. The method increasing a mol percent of nitride with respect to a total tantalum plus nitride to 25% or greater during a barrier layer fabrication process.Type: GrantFiled: February 22, 2008Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Felix P. Anderson, Steven P. Barkyoumb, Edward C. Cooney, III, Thomas L. McDevitt, William J. Murphy, David C. Strippe
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Patent number: 8927411Abstract: A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.Type: GrantFiled: December 27, 2013Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Felix P. Anderson, Timothy H. Daubenspeck, Jeffrey P. Gambino, Timothy S. Hayes, Donald R. Letourneau, Thomas L. McDevitt, Anthony K. Stamper
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Patent number: 8921975Abstract: A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.Type: GrantFiled: June 5, 2012Date of Patent: December 30, 2014Assignee: International Business Machines CorporationInventors: Felix P. Anderson, Timothy H. Daubenspeck, Jeffrey P. Gambino, Timothy S. Hayes, Donald R. Letourneau, Thomas L. McDevitt, Anthony K. Stamper
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Patent number: 8878315Abstract: A MEMS structure and methods of manufacture. The method includes forming a sacrificial metal layer at a same level as a wiring layer, in a first dielectric material. The method further includes forming a metal switch at a same level as another wiring layer, in a second dielectric material. The method further includes providing at least one vent to expose the sacrificial metal layer. The method further includes removing the sacrificial metal layer to form a planar cavity, suspending the metal switch. The method further includes capping the at least one vent to hermetically seal the planar cavity.Type: GrantFiled: February 15, 2013Date of Patent: November 4, 2014Assignee: International Business Machines CorporationInventors: Felix P. Anderson, Thomas L. McDevitt, Anthony K. Stamper
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Patent number: 8791778Abstract: Vertical integrated MEMS switches, design structures and methods of fabricating such vertical switches is provided herein. The method of manufacturing a MEMS switch, includes forming at least two vertically extending vias in a wafer and filling the at least two vertically extending vias with a metal to form at least two vertically extending wires. The method further includes opening a void in the wafer from a bottom side such that at least one of the vertically extending wires is moveable within the void.Type: GrantFiled: September 16, 2013Date of Patent: July 29, 2014Assignee: International Business Machines CorporationInventors: Felix P. Anderson, Edward C. Cooney, III, Thomas L. McDevitt, Anthony K. Stamper
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Publication number: 20140106559Abstract: A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.Type: ApplicationFiled: December 27, 2013Publication date: April 17, 2014Applicant: International Business Machines CorporationInventors: Felix P. Anderson, Timothy H. Daubenspeck, Jeffrey P. Gambino, Timothy S. Hayes, Donald R. Letourneau, Thomas L. McDevitt, Anthony K. Stamper
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Publication number: 20140017844Abstract: Integrated MEMS switches, design structures and methods of fabricating such switches are provided. The method includes forming at least one tab of sacrificial material on a side of a switching device which is embedded in the sacrificial material. The method further includes stripping the sacrificial material through at least one opening formed on the at least one tab which is on the side of the switching device, and sealing the at least one opening with a capping material.Type: ApplicationFiled: September 16, 2013Publication date: January 16, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Felix P. ANDERSON, Thomas L. McDevitt, Anthony K. Stamper
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Publication number: 20140014480Abstract: Vertical integrated MEMS switches, design structures and methods of fabricating such vertical switches is provided herein. The method of manufacturing a MEMS switch, includes forming at least two vertically extending vias in a wafer and filling the at least two vertically extending vias with a metal to form at least two vertically extending wires. The method further includes opening a void in the wafer from a bottom side such that at least one of the vertically extending wires is moveable within the void.Type: ApplicationFiled: September 16, 2013Publication date: January 16, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Felix P. ANDERSON, Edward C. COONEY, III, Thomas L. MCDEVITT, Anthony K. STAMPER
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Patent number: 8604898Abstract: Vertical integrated MEMS switches, design structures and methods of fabricating such vertical switches is provided herein. The method of manufacturing a MEMS switch, includes forming at least two vertically extending vias in a wafer and filling the at least two vertically extending vias with a metal to form at least two vertically extending wires. The method further includes opening a void in the wafer from a bottom side such that at least one of the vertically extending wires is moveable within the void.Type: GrantFiled: April 20, 2009Date of Patent: December 10, 2013Assignee: International Business Machines CorporationInventors: Felix P. Anderson, Edward C. Cooney, III, Thomas L. McDevitt, Anthony K. Stamper
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Publication number: 20130320488Abstract: A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.Type: ApplicationFiled: June 5, 2012Publication date: December 5, 2013Applicant: International Business Machines CorporationInventors: Felix P. Anderson, Timothy H. Daubenspeck, Jeffrey P. Gambino, Timothy S. Hayes, Donald R. Letourneau, Thomas L. McDevitt, Anthony K. Stamper
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Patent number: 8569091Abstract: Integrated MEMS switches, design structures and methods of fabricating such switches are provided. The method includes forming at least one tab of sacrificial material on a side of a switching device which is embedded in the sacrificial material. The method further includes stripping the sacrificial material through at least one opening formed on the at least one tab which is on the side of the switching device, and sealing the at least one opening with a capping material.Type: GrantFiled: August 27, 2009Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Felix P. Anderson, Thomas L. McDevitt, Anthony K. Stamper
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Patent number: 8535966Abstract: A MEMS structure and methods of manufacture. The method includes forming a sacrificial metal layer at a same level as a wiring layer, in a first dielectric material. The method further includes forming a metal switch at a same level as another wiring layer, in a second dielectric material. The method further includes providing at least one vent to expose the sacrificial metal layer. The method further includes removing the sacrificial metal layer to form a planar cavity, suspending the metal switch. The method further includes capping the at least one vent to hermetically seal the planar cavity.Type: GrantFiled: July 27, 2010Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: Felix P. Anderson, Thomas L. McDevitt, Anthony K. Stamper