Patents by Inventor Feng-Cheng Jeng

Feng-Cheng Jeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153840
    Abstract: A method for forming a package structure is provided. The method includes disposing a semiconductor die over a carrier substrate, wherein a removable film is formed over the semiconductor die, disposing a first stacked die package structure over the carrier substrate, wherein a top surface of the removable film is higher than a top surface of the first stacked die package structure, and removing the removable film to expose a top surface of the semiconductor die, wherein a top surface of the semiconductor die is lower than the top surface of the first stacked die package structure.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 9, 2024
    Inventors: Shin-Puu JENG, Po-Yao LIN, Feng-Cheng HSU, Shuo-Mao CHEN, Chin-Hua WANG
  • Patent number: 11948914
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a package substrate, a semiconductor chip disposed over the package substrate, and an integrated device located below and bonded to the lower surface of the semiconductor chip. The semiconductor chip has a lower surface facing the package substrate and is electrically connected to the package substrate through conductive structures. The integrated device is laterally surrounded by the conductive structures, and the integrated device and the conductive structures are located within boundaries of the semiconductor chip when viewed in a direction perpendicular to the lower surface of the semiconductor chip.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng-Cheng Hsu, Shin-Puu Jeng, Shuo-Mao Chen
  • Patent number: 11942408
    Abstract: A method includes: bonding a plurality of interposer dies to a first redistribution layer (RDL), each of the interposer dies comprising a substrate and a second RDL below the substrate; encapsulating the first RDL and the interposer dies; reducing a thickness of the substrate of each of the interposer dies; and electrically coupling the interposer dies to a first semiconductor die.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Shin-Puu Jeng
  • Publication number: 20240096731
    Abstract: A semiconductor package is provided, which includes a first chip disposed over a first package substrate, a molding compound surrounding the first chip, a first thermal interface material disposed over the first chip and the molding compound, a heat spreader disposed over the thermal interface material, and a second thermal interface material disposed over the heat spreader. The first thermal interface material and the second thermal interface material have an identical width.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Chin-Hua WANG, Po-Yao LIN, Feng-Cheng HSU, Shin-Puu JENG, Wen-Yi LIN, Shu-Shen YEH
  • Publication number: 20240088124
    Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
  • Publication number: 20240087903
    Abstract: Provided is a package structure including a die, a through via, an encapsulant, a warpage controlling layer, and a cap. The through via is laterally aside the die. The encapsulant laterally encapsulates the through via and the die. The warpage controlling layer covers the encapsulant and the die. The cap is laterally aside the warpage controlling layer and on the through via. The cap has a top surface higher than a top surface of the encapsulant and lower than a top surface of the warpage controlling layer.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng
  • Patent number: 11915992
    Abstract: A method for forming a package structure is provided, including forming an interconnect structure over a carrier substrate and forming a semiconductor die over a first side of the interconnect structure. A removable film is formed over the semiconductor die. The method includes forming a first stacked die package structure over the first side of the interconnect structure. A top surface of the removable film is higher than a top surface of the first stacked die package structure. The method includes forming a package layer, removing a portion of the package layer to expose a portion of the removable film, removing the removable film to form a recess, forming a lid structure over the semiconductor die and the first stacked die package structure. The lid structure has a main portion and a protruding portion disposed in the recess and extending from the main portion.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Puu Jeng, Po-Yao Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Chin-Hua Wang
  • Patent number: 6692985
    Abstract: A solar cell substrate with thin film polysilicon. The solar cell substrate includes a substrate; a transparent conductive layer, formed on the substrate; a thermal isolation layer having inlaid conductive layers, formed on the transparent conductive layer; and a polysilicon layer, formed on the thermal isolation layer.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: February 17, 2004
    Assignee: Industrial Technology Research Institute
    Inventors: Chorng-Jye Huang, Lee Ching Kuo, Jyi Tyan Yeh, Chien Sheng Huang, Leo C. K. Liau, Shih-Chen Lin, Cheng-Ting Chen, Feng-Cheng Jeng
  • Publication number: 20020185171
    Abstract: A solar cell substrate with thin film polysilicon. The solar cell substrate includes a substrate; a transparent conductive layer, formed on the substrate; a thermal isolation layer having inlaid conductive layers, formed on the transparent conductive layer; and a polysilicon layer, formed on the thermal isolation layer.
    Type: Application
    Filed: June 7, 2002
    Publication date: December 12, 2002
    Inventors: Chorng-Jye Huang, Lee-Ching Kuo, Jyi-Tyan Yeh, Chien-Sheng Huang, Leo C.K. Liau, Shih-Chen Lin, Cheng-Ting Chen, Feng-Cheng Jeng