Abstract: An electronic switch device and an electronic switch system are provided, wherein the electronic switch system includes: an electronic switch device, which includes: a sensing module, which includes: a pressure sensing module for providing a pressure sensing signal; and a touch control sensing module disposed on the pressure sensing module for providing a touch control sensing signal; and a comparator circuit coupled to the sensing module for receiving the pressure sensing signal.

Abstract: A method includes the following steps: a first step: the material containing heteroatom and graphite powder are mixed for a preset time by grinding, and the molar ratio of heteroatom to carbon atom is 1%-10%, then the heteroatom precursors are obtained; a second contact step: the heteroatom precursor is filled into a graphite rod with holes and compacted, then the graphite rod is dried for a preset time to obtain a plasma anode and using a DC arc plasma device to prepare the graphite anode into heteroatom-doped CNHs; a third contact step: the heteroatom-doped CNHs are dispersed in a reducing solution, a platinum salt is added to stir evenly, the reduction reaction is carried out by heating and stirring, and after centrifugation, washing and drying, a catalyst with platinum loading is obtained.

Abstract: The present invention relates to a low-temperature co-fired ceramic powder and a preparation method and application thereof. The material composition of the low-temperature co-fired ceramic powder is xRO-yM2O3-zXO2, where R is at least one of Mg, Ca, Ba, Zn, Cu, and Pb, M is at least one of B, Al, Co, In, Bi, Nd, Sm, and La, X is at least one of Si, Ge, Sn, Ti, Zr, and Hf, 0?x?85 wt %, 15 wt %?y?90 wt %, 10 wt %?z?85 wt %, and x+y+z=1; and the low-temperature co-fired ceramic powder is obtained by high-temperature melting, quenching, and recrystallization treatment. The temperature of high-temperature melting is 1,200° C. to 1,600° C., and the temperature of recrystallization treatment is 500° C. to 900° C.

Abstract: Provided in embodiments of this application are a transmission assembly and a foldable electronic device. The transmission assembly includes a first transmission assembly. The first transmission assembly is configured for use in a bending area of the foldable electronic device. The first transmission assembly includes at least two first conductive layers and a first transmission layer located between the two first conductive layers. Each first conductive layer includes at least a first conductive fabric, and the first transmission layer includes at least one first signal line. A dielectric layer is further arranged between the first conductive layer and the first transmission layer, and the dielectric layer includes at least a first substrate layer.

Abstract: A rotor includes a rotor core lamination. The rotor core lamination includes a first metal alloy that at least partially defines adjacent magnet pockets proximate an outer periphery of the rotor core lamination. The rotor core lamination further includes a second metal alloy different than the first metal alloy that forms at least a portion of a bridge that extends between the magnet pockets. The rotor core lamination further includes permanent magnets disposed in the magnet pockets at opposing sides of the second metal alloy.

Abstract: Provided is a semiconductor device including a substrate having a lower portion and an upper portion on the lower portion; an isolation region disposed on the lower portion of the substrate and surrounding the upper portion of the substrate in a closed path; a gate structure disposed on and across the upper portion of the substrate; source and/or drain (S/D) regions disposed in the upper portion of the substrate at opposite sides of the gate structure; and a channel region disposed below the gate structure and abutting between the S/D regions, wherein the channel region and the S/D regions have different conductivity types, and the channel region and the substrate have the same conductivity type.

Abstract: A retinomorphic sensor array and a convolution method are used for image processing therefor, wherein the optoelectronic sensor has a vertically stacked heterostructure provided with a bottom electrode, a dielectric layer, a channel layer, a source electrode and a drain electrode on a base, the source and drain electrode are mutually opposite and are arranged at two ends of the channel layer, the bottom electrode, the source and drain electrode are made of a material used by a flexible electrode, an inert metal or a semimetal, the dielectric layer is made of an insulating material, the channel layer is made of a bipolar material, and the base comprises a substrate and an insulating material layer generated on a surface of the substrate.

Abstract: An energy storage device includes a current collecting member. The current collecting member includes an adapter and an insulator, the adapter includes a first connecting portion, a fuse portion, and a second connecting portion, and the ratio of the width of the fuse portion to the width of the first connecting portion is in a range from ? to ?. The first connecting portion is provided with first corners, and the second connecting portion is provided with second corners. The insulator is provided with a first protective portion, a second protective portion and a third protective portion. The first protective portion covers the first corners, the second protective portion covers the second corners, the third protective portion covers a first surface of the fuse portion of the adapter, and a second surface of the fuse portion is at least partially exposed from the insulator.

Abstract: An electric machine includes a stator core defining slots and a first hairpin assembly installed in the stator core. The first hairpin assembly includes first and second same hairpins, each having first and second ends and separately coated to have first and second outer coating surfaces, respectively. The hairpin assembly is in first and second ones of the slots such that the first and second outer surfaces are touching. A weld material joins the first ends and another weld material joins the second ends.

Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.

Abstract: Various example embodiments described herein relate to a sensor assembly. The sensor assembly includes a first sensor cover and a second sensor cover. The first sensor cover is disposed on a first end of the sensor assembly and the second sensor cover is disposed on a second end of the sensor assembly. The first sensor cover defines a first capillary and the second sensor cover defines a second capillary therethrough. The sensor assembly further includes a first sensing unit, a second sensing unit, and a filter. The first sensing unit and the second sensing unit are disposed between the first sensor cover and the second sensor cover. In some example embodiments, the filter is reactive to a target gas and thereby prevents an inflow of the target gas through the second capillary into the sensor assembly.

Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.

Abstract: A method and a system for consolidating a subterranean formation are provided. An exemplary method includes injecting a water-in-oil emulsion into an unconsolidated subterranean formation, wherein the water-in-oil emulsion includes comonomers in an oil phase to form a polyurethane resin, and a catalyst in an aqueous phase. The method also includes allowing the polyurethane resin to cure to form a porous polymeric network.

Abstract: Disclosed are a display apparatus, a drive chip, and an electronic device. When determining that a disconnected signal line exists, the drive chip sends a control signal to a signal line repair module, so that when a shift output end of the first shift unit corresponding to the disconnected signal line outputs an enable signal, a selector switch corresponding to the shift output end is turned on, and then a connection control unit keeps outputting a turn-on signal to a control end of a corresponding connection switch.

Abstract: A treatment fluid composition includes a carrier fluid and a curable hybrid resin. The curable hybrid resin includes a first curable resin (A) including a reactive silyl group that reacts with water downhole, a second curable resin (B), and a curing agent for the second curable resin (B). A method of treating a subterranean formation includes injecting a treatment fluid including a curable hybrid resin into a target zone of the subterranean formation. The target zone may have unconsolidated or weakly consolidated sand. The method then includes maintaining the treatment fluid in the target zone for a period of time such that the curable hybrid resin cures and forming a consolidated formation in the target zone.

Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.

Abstract: Some embodiments of this specification disclose a knowledge graph construction method and system. The method includes: obtaining ontology definition data of a knowledge graph, where the ontology definition data includes node definition data of a plurality of nodes, the node definition data includes a node attribute value type, the node attribute value type is a basic type, a standard type, or a concept type, the basic type is used to represent a data type of an attribute value, the standard type is used to represent a fixed format of the attribute value, and the concept type is used to represent a multi-level structure of the attribute value; and processing instance data based on the ontology definition data to obtain the knowledge graph that includes a node instance of a standard type attribute value and/or a concept type attribute value.

Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.

Abstract: Disclosed are a display apparatus, a drive chip, and an electronic device. When determining that a disconnected signal line (DL) exists, a drive chip sends a control signal to a signal line repair module, so that shift output ends (OUT) of a plurality of shift units sequentially output enable signals, and the shift unit corresponding to a connection switch electrically connected to the disconnected signal line (DL) continuously outputs enable signals, so that the connection switch electrically connected to the disconnected signal line (DL) is continuously turned on. The display apparatus may repair a disconnected signal line without being returned to a factory and a manual operation.

Abstract: A magnet structure includes columnar grains of rare earth permanent magnet phase aligned in a same direction and arranged to form bulk anisotropic rare earth alloy magnet having a boundary defined by opposite ends of the columnar grains and lacking triple junction regions, and rare earth alloy diffused onto opposite ends of the bulk anisotropic rare earth alloy magnet.