Patents by Inventor Feng Liao
Feng Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240190116Abstract: A polyolefin packaging material includes a first polyolefin polymer film, a second polyolefin polymer film, and a polyolefin bonding adhesive layer. The first polyolefin polymer film is a cast polypropylene film (CPP film). The second polyolefin polymer film is a biaxially oriented polypropylene film (BOPP film). The polyolefin bonding adhesive layer is bonded between the first polyolefin polymer film and the second polyolefin polymer film. The polyolefin bonding adhesive layer is formed of a polyolefin copolymer modified by maleic anhydride, the polyolefin copolymer is formed by copolymerization of at least two kinds of C2 to C4 olefin molecules, a graft ratio of the maleic anhydride grafted onto the polyolefin copolymer is between 0.5% and 5%, and a melt index of the polyolefin copolymer is between 1 g/10 min and 5 g/10 min.Type: ApplicationFiled: April 6, 2023Publication date: June 13, 2024Inventors: TE-CHAO LIAO, CHING-YAO YUAN, Chih-Feng Wang, TENG-KO MA
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Publication number: 20240191104Abstract: A polyolefin bonding adhesive film includes a support base layer and a bonding adhesive layer formed on a side surface of the support base layer by co-extrusion. The support base layer is a polypropylene film. The bonding adhesive layer is formed of a first polyolefin copolymer modified by maleic anhydride. The first polyolefin copolymer is formed by copolymerization of at least two kinds of C2 to C4 olefin molecules, a first graft ratio of the maleic anhydride grafted onto the first polyolefin copolymer is between 0.5% and 5%, and a first melt index of the first polyolefin copolymer is between 3 g/10 min and 5 g/10 min.Type: ApplicationFiled: April 9, 2023Publication date: June 13, 2024Inventors: Te-Chao Liao, Ching-Yao Yuan, Chih-Feng Wang, Teng-Ko Ma
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Patent number: 12009400Abstract: A method includes forming a dielectric layer on a semiconductor workpiece, forming a first patterned layer of a first dipole material on the dielectric layer, and performing a first thermal drive-in operation at a first temperature to form a diffusion feature in a first portion of the dielectric layer beneath the first patterned layer. The method also includes forming a second patterned layer of a second dipole material, where a first section of the second patterned layer is on the diffusion feature and a second section of the second patterned layer is offset from the diffusion feature. The method further includes performing a second thermal drive-in operation at a second temperature, where the second temperature is less than the first temperature. The method additionally includes forming a gate electrode layer on the dielectric layer.Type: GrantFiled: September 1, 2021Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Hsiang Chan, Shan-Mei Liao, Wen-Hung Huang, Jian-Hao Chen, Kuo-Feng Yu, Mei-Yun Wang
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Patent number: 12005711Abstract: The method of the present disclosure includes steps of: (S1) providing a silicon substrate; (S2) arranging and disposing an active component layer by utilizing a first type photomask on at least two high-precision regions of each of a plurality of inkjet print head chip regions on the silicon substrate; (S3) arranging and disposing a passive component layer by utilizing a second type photomask on the active component layer; and (S4) cutting the silicon substrate according to the inkjet print head chip regions so as to form the plurality of narrow type inkjet print head chips.Type: GrantFiled: March 18, 2021Date of Patent: June 11, 2024Assignee: MICROJET TECHNOLOGY CO., LTD.Inventors: Hao-Jan Mou, Rong-Ho Yu, Cheng-Ming Chang, Hsien-Chung Tai, Wen-Hsiung Liao, Chi-Feng Huang, Yung-Lung Han
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Patent number: 12010004Abstract: A system manages a network using a graphical user interface (GUI) that maps the network. The mapping includes a topology of network layers and includes the generation of a path through the network, which may use virtualization technology. The path may be an AB network path that is automatically discovered and may be compared with a golden path.Type: GrantFiled: July 19, 2019Date of Patent: June 11, 2024Assignee: NetBrain Technologies, Inc.Inventors: Lingping Gao, Guangdong Liao, Feng Gan, Yanguo Guo, Xinfeng Xia, Dezhi Chen, Nong Jiang
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Publication number: 20240186188Abstract: A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.Type: ApplicationFiled: February 14, 2024Publication date: June 6, 2024Inventors: Yung-Hsiang CHAN, Wen-Hung HUANG, Shan-Mei LIAO, Jian-Hao CHEN, Kuo-Feng YU, Kuei-Lun LIN
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Publication number: 20240182651Abstract: Provided is a hydrogel composition, which comprises a modified HA, PEGDA and water; wherein, based on a total weight of the hydrogel composition, a content of the modified HA is 1 wt % to 7 wt % and a content of PEGDA is 43 wt % to 49 wt %; the modified HA is obtained by modifying HA with methacrylic anhydride; an average molecular weight of PEGDA is 1 kDa to 10 kDa. The hydrogel composition of the present invention has good compatibility of raw materials, which does not cause HA precipitation, and a hydrogel material produced therefrom simultaneously has good mechanical properties, good swell capability and good biocompatibility, such that the hydrogel material can be applied in many fields.Type: ApplicationFiled: February 14, 2023Publication date: June 6, 2024Inventors: Ta-Jo LIU, Hsiu-Feng YEH, Shin-Yi YIN, Yi-Jyun LIAO, Ying-Hua HSU
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Publication number: 20240186308Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a redistribution layer (RDL) module, a first semiconductor module, an interconnection module, a second semiconductor module and a molding material. The first semiconductor module is disposed on the RDL module. The interconnection module is disposed on the RDL module. The second semiconductor module is disposed on the interconnection module. The molding material covers the RDL module and surrounds the first semiconductor module and the second semiconductor module. A top surface of the first semiconductor module and a top surface of the second semiconductor module are exposed by the molding material.Type: ApplicationFiled: January 19, 2023Publication date: June 6, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, CHEYU LIU, Hung-Chih CHEN, Yi-Yang LEI, CHING-HUA HSIEH, Hung-Chou LIAO
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Publication number: 20240174367Abstract: The present application provides a system for unmanned aerial vehicle (UAV) parachute landing. An exemplary system includes a detector configured to detect at least one of a flight speed, a wind speed, a wind direction, a position, a height, and a voltage of a UAV. The system also includes a memory storing instructions and a processor configured to execute the instructions to cause the system to: determine whether to open a parachute of the UAV in accordance with a criterion, responsive to the determination to open the parachute of the UAV, stop a motor of the UAV that spins a propeller of the UAV, and open the parachute of the UAV after stopping the motor of the UAV for a first period.Type: ApplicationFiled: December 22, 2023Publication date: May 30, 2024Applicant: GEOSAT Aerospace & TechnologyInventors: Lung-Shun SHIH, Fu-Kai YANG, Yi-Feng CHENG, Di-Yang WANG, Chien-Hsun LIAO
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Publication number: 20240175920Abstract: The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies, and a benchmark circuit disposed on the scribe line. The benchmark circuit includes a first switching circuit, a first process control monitoring (PCM) device and a second PCM device coupled to the first switching circuit, and a second switching circuit. The first switching circuit is configured to selectively couple the first PCM device and the second PCM device to receive a test signal, wherein the first PCM device and the second PCM device are configured to output a first output signal and a second output signal in response to the test signal, respectively. The second switching circuit is configured to selectively couple the first PCM device and the second PCM device to output the first output signal or the second output signal.Type: ApplicationFiled: February 6, 2024Publication date: May 30, 2024Inventors: CHU-FENG LIAO, HUNG-PING CHENG, YUAN-YAO CHANG, SHUO-WEN CHANG
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Patent number: 11994534Abstract: A testing device for testing an integrated circuit package is provided, including a printed circuit board, a testing socket, a conductive fastener, a cover, and a conductive element assembly. The printed circuit board includes a first metal layer formed on the bottom surface thereof. The testing socket is disposed above the printed circuit board. The conductive fastener is configured to secure the testing socket to the printed circuit board, wherein the conductive fastener is electrically connected to the first metal layer and the testing socket. The cover is disposed above the testing socket to form a space for accommodating the integrated circuit package between the cover and the testing socket, wherein the cover makes electrical contact with the integrated circuit package. The conductive element assembly is disposed between and electrically connected to the cover and the testing socket.Type: GrantFiled: March 13, 2023Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shao-Chun Chiu, Wen-Feng Liao, Hao Chen, Chun-Hsing Chen
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Publication number: 20240170385Abstract: A semiconductor package device is provided. The semiconductor package device includes a chip and a redistribution layer disposed on the chip and electrically connected to the chip. The redistribution layer includes a plurality of first metal lines and a plurality of second metal lines, wherein at least one of the second metal lines is disposed between two adjacent first metal lines. The included angle between the at least one of the second metal lines and the two adjacent first metal lines is greater than or equal to 0 degrees and less than or equal to 10 degrees. The first width of one of the two adjacent first metal lines is greater than the second width of the at least one of the second metal lines.Type: ApplicationFiled: December 22, 2022Publication date: May 23, 2024Inventors: Te-Hsun LIN, Wen-Hsiang LIAO, Mei-Yen CHEN, Ming-Hsien SHIH, Yung-Feng CHEN, Cheng-Chi WANG
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Patent number: 11991882Abstract: A method for fabricating a memory device includes: providing a substrate; forming a first dielectric layer over the substrate; forming a plurality of conductive layers and a plurality of dielectric layers alternately and horizontally disposed on the substrate; forming a channel column structure on the substrate and in the plurality of conductive layers and the plurality of dielectric layers, where a side wall of the channel column structure is in contact with the plurality of conductive layers; forming a second dielectric layer covering the first dielectric layer; and forming, in the first and second dielectric layers, a conductive column structure adjacent to the channel column structure and in contact with one of the plurality of conductive layers, where the conductive column structure includes a liner insulating layer as a shell layer.Type: GrantFiled: November 16, 2021Date of Patent: May 21, 2024Assignee: MACRONIX International Co., Ltd.Inventors: Yao-An Chung, Yuan-Chieh Chiu, Ting-Feng Liao, Kuang-Wen Liu, Kuang-Chao Chen
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Publication number: 20240161410Abstract: Various implementations disclosed herein include devices, systems, and methods that generate floorplans and measurements using a three-dimensional (3D) representation of a physical environment generated based on sensor data.Type: ApplicationFiled: January 25, 2024Publication date: May 16, 2024Inventors: Feng Tang, Afshin Dehghan, Kai Kang, Yang Yang, Yikang Liao, Guangyu Zhao
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Publication number: 20240154115Abstract: A lithium-ion battery includes a positive electrode plate, a negative electrode plate, a separator, and an electrolyte; the positive electrode plate includes a positive electrode current collector and a positive electrode material, the positive electrode material includes a lithium supplement additive LixMyOz, which is selected from one or more of the following formulas I-V; and/or one or more of halogenated compounds of the following formulas I-V; where, in formula I, R1 is selected from one of substituted or unsubstituted C1-6 alkylene group and substituted or unsubstituted C2-6 alkenylene group; in formula II, R2 is selected from one of substituted or unsubstituted C1-6 alkylene group and substituted or unsubstituted C2-6 alkenylene group.Type: ApplicationFiled: December 13, 2023Publication date: May 9, 2024Inventors: Changming Zhang, Dalin Hu, Xingqun Liao, Feng Li
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Publication number: 20240153860Abstract: An electronic device is provided. The electronic device includes a redistribution structure, an electronic unit and a first conductive pad. The first conductive pad is disposed between the redistribution structure and the electronic unit. The electronic unit is electrically connected to the redistribution structure through the first conductive pad. The first conductive pad has a first coefficient of thermal expansion and a first Young's modulus. The first coefficient of thermal expansion and the first Young's modulus conform to the following formula: 0.7×(0.0069E2?1.1498E+59.661)?CTE?1.3×(0.0069E2?1.1498E+59.661), wherein CTE is the first coefficient of thermal expansion, and E is the first Young's modulus in the formula.Type: ApplicationFiled: December 21, 2022Publication date: May 9, 2024Inventors: Te-Hsun LIN, Wen-Hsiang LIAO, Yung-Feng CHEN, Ming-Hsien SHIH
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Publication number: 20240146002Abstract: An electrical connector includes an insulating housing, a plurality of first terminals, a plurality of second terminals, a metal element and a fastening assembly. The insulating housing has a first insulating body, a second insulating body surrounding the first insulating body, a third insulating body and a fourth insulating body. The third insulating body is disposed to a rear end of a top surface of the first insulating body. The fourth insulating body is disposed to a top surface of the third insulating body. The plurality of the first terminals are surrounded by the first insulating body and the second insulating body. The plurality of the second terminals are surrounded by the third insulating body. The metal element is disposed to an outer surface of the insulating housing. The fastening assembly is positioned above the fourth insulating body.Type: ApplicationFiled: September 12, 2023Publication date: May 2, 2024Inventors: XU LIU, BIN WANG, TING-FENG LIAO
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Publication number: 20240145370Abstract: A semiconductor device includes a first region and a second region, and the second region surrounds the first region. The semiconductor device includes at least one electronic unit, a redistribution structure, a plurality of first pads, and a plurality of second pads. The redistribution structure may be electrically connected to at least one electronic unit. A plurality of first pads are arranged on the redistribution structure and correspondingly to the first region. There is a first pitch between two adjacent first pads. A plurality of second pads are arranged on the redistribution structure and correspondingly to the second region. There is a second pitch between two adjacent second pads, so that the first pitch is smaller than the second pitch.Type: ApplicationFiled: December 18, 2022Publication date: May 2, 2024Applicant: InnoLux CorporationInventors: Te-Hsun LIN, Wen-Hsiang LIAO, Ming-Hsien SHIH, Yung-Feng CHEN, Cheng-Chi WANG
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Patent number: 11972717Abstract: Embodiments of the present disclosure provide a method of driving display, and a display device. The method of driving display includes: scanning, progressively or rows by rows, a plurality of sub-pixels arranged in an N×M array, to turn on each row of sub-pixels scanned, so that a duration in which two adjacent rows of sub-pixels are simultaneously in an ON state is greater than or equal to two times a unit scanning time, wherein the unit scanning time is a time required for scanning a row of sub-pixels, N is an integer greater than 1, and M is an integer greater than 1; and applying data signals to at least two rows of sub-pixels simultaneously in the ON state, so that a duration of applying the data signals to each row of sub-pixels is greater than the unit scanning time.Type: GrantFiled: March 13, 2023Date of Patent: April 30, 2024Assignees: Beijing BOE Display Technology Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Zhihua Sun, Yinlong Zhang, Qiujie Su, Feng Qu, Jing Liu, Yanping Liao, Xibin Shao
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Patent number: 11972072Abstract: The present disclosure provides an electronic device including a first sensing circuit, a second sensing circuit and a power line. The first sensing circuit includes a first sensing unit and a first transistor, and a first end of the first sensing unit is coupled to a control end of the first transistor. The second sensing circuit includes a second sensing unit and a second transistor, and a first end of the second sensing unit is coupled to a control end of the second transistor. A first end of the first transistor and a first end of the second transistor are coupled to the power line.Type: GrantFiled: November 1, 2022Date of Patent: April 30, 2024Assignee: InnoLux CorporationInventors: Shu-Fen Li, Chuan-Chi Chien, Hsiao-Feng Liao, Rui-An Yu, Chang-Chiang Cheng, Po-Yang Chen, I-An Yao