Patents by Inventor Feng Lung Lin
Feng Lung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11936198Abstract: A wireless device is provided and includes a substrate, a first coil and a second coil. The first coil is configured to be wound around a first axis, and the first coil is disposed on the substrate and is configured to operate in a wireless charging mode. The second coil is disposed on the substrate and configured to operate in a wireless communication mode. The wires of the second coil partially overlap the wires of the first coil.Type: GrantFiled: May 21, 2021Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Feng-Lung Chien, Hsiang-Hui Hsu, Chien-Hung Lin
-
Patent number: 10747938Abstract: An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.Type: GrantFiled: July 19, 2019Date of Patent: August 18, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chun Wang, Ching-Hsu Chang, Chun-Hung Wu, Cheng Kun Tsai, Feng-Ju Chang, Feng-Lung Lin, Ming-Hsuan Wu, Ping-Chieh Wu, Ru-Gun Liu, Wen-Chun Huang, Wen-Hao Liu
-
Publication number: 20190340330Abstract: An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.Type: ApplicationFiled: July 19, 2019Publication date: November 7, 2019Inventors: Hung-Chun Wang, Ching-Hsu Chang, Chun-Hung Wu, Cheng Kun Tsai, Feng-Ju Chang, Feng-Lung Lin, Ming-Hsuan WU, Ping-Chieh Wu, Ru-Gun Liu, Wen-Chun Huang, Wen-Hao Liu
-
Patent number: 10360339Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.Type: GrantFiled: February 15, 2016Date of Patent: July 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Chun Wang, Ching-Hsu Chang, Chun-Hung Wu, Cheng Kun Tsai, Feng-Ju Chang, Feng-Lung Lin, Ming-Hsuan Wu, Ping-Chieh Wu, Ru-Gun Liu, Wen-Chun Huang, Wen-Hao Liu
-
Publication number: 20160162627Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.Type: ApplicationFiled: February 15, 2016Publication date: June 9, 2016Inventors: Hung-Chun Wang, Ching-Hsu Chang, Chun-Hung Wu, Cheng Kun Tsai, Feng-Ju Chang, Feng-Lung Lin, Ming-Hsuan WU, Ping-Chieh Wu, Ru-Gun Liu, Wen-Chun Huang, Wen-Hao Liu
-
Patent number: 9262578Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.Type: GrantFiled: June 2, 2014Date of Patent: February 16, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chun Wang, Ching-Hsu Chang, Feng-Ju Chang, Chun-Hung Wu, Ping-Chieh Wu, Wen-Hao Liu, Ming-Hsuan Wu, Feng-Lung Lin, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
-
Publication number: 20150310158Abstract: Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.Type: ApplicationFiled: June 2, 2014Publication date: October 29, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Chun Wang, Ching-Hsu Chang, Feng-Ju Chang, Chun-Hung Wu, Ping-Chieh Wu, Wen-Hao Liu, Ming-Hsuan Wu, Feng-Lung Lin, Cheng Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
-
Patent number: 8202681Abstract: A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.Type: GrantFiled: July 21, 2011Date of Patent: June 19, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Lung Lin, Kuan-Liang Wu, Che-Rong Liang, Fei-Gwo Tsai
-
Publication number: 20110281208Abstract: A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.Type: ApplicationFiled: July 21, 2011Publication date: November 17, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng-Lung Lin, Kuan-Liang Wu, Fei-Gwo Tsai, Che-Rong Liang
-
Patent number: 8007966Abstract: A method of fabricating a mask set is provided. The method includes providing mask data associated with a plurality of mask layers. The mask data includes a first pattern associated with a first technology node and a second pattern associated with a second technology node. The method continues with determining to form a multi-technology node mask (MTM) for a first mask layer of the plurality of mask layers. The MTM for the first mask layer is formed, which includes features associated with the first pattern and features associated with the second pattern.Type: GrantFiled: January 14, 2011Date of Patent: August 30, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Lung Lin, Kuan Liang Wu, Fei-Gwo Tsai, Che-Rong Liang
-
Patent number: 8003281Abstract: A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.Type: GrantFiled: October 13, 2008Date of Patent: August 23, 2011Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Feng-Lung Lin, Kuan-Liang Wu, Che-Rong Liang, Fei-Gwo Tsai
-
Publication number: 20110113389Abstract: A method of fabricating a mask set is provided. The method includes providing mask data associated with a plurality of mask layers. The mask data includes a first pattern associated with a first technology node and a second pattern associated with a second technology node. The method continues with determining to form a multi-technology node mask (MTM) for a first mask layer of the plurality of mask layers. The MTM for the first mask layer is formed, which includes features associated with the first pattern and features associated with the second pattern.Type: ApplicationFiled: January 14, 2011Publication date: May 12, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng Lung Lin, Kuan Liang Wu, Fei-Gwo Tsai, Che-Rong Liang
-
Patent number: 7875406Abstract: A multiple technology node mask (MTM) is provided. An MTM includes a pattern associated with a first technology node and a pattern associated with a second technology node. The first technology node and the second technology node may be different. For example, the first technology node may be a main node and the second technology node a sub-node. A mask set including an MTM may also include single technology node masks (STMs) for mask layers in which the first technology node and second technology node and/or the patterns associated with each are not compatible. A single mask set including MTM and STMs, may be used to produce a plurality of devices, each on a different wafer.Type: GrantFiled: March 27, 2008Date of Patent: January 25, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Lung Lin, Kuan Liang Wu, Fei-Gwo Tsai, Che-Rong Liang
-
Publication number: 20100047698Abstract: A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.Type: ApplicationFiled: October 13, 2008Publication date: February 25, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng-Lung Lin, Kuan-Liang Wu, Che-Rong Liang, Fei-Gwo Tsai
-
Publication number: 20090246975Abstract: A multiple technology node mask (MTM) is provided. An MTM includes a pattern associated with a first technology node and a pattern associated with a second technology node. The first technology node and the second technology node may be different. For example, the first technology node may be a main node and the second technology node a sub-node. A mask set including an MTM may also include single technology node masks (STMs) for mask layers in which the first technology node and second technology node and/or the patterns associated with each are not compatible. A single mask set including MTM and STMs, may be used to produce a plurality of devices, each on a different wafer.Type: ApplicationFiled: March 27, 2008Publication date: October 1, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng Lung Lin, Kuan Liang Wu, Fei-Gwo Tsai, Che-Rong Liang