Patents by Inventor Feng-Ming Wang
Feng-Ming Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240164109Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.Type: ApplicationFiled: January 8, 2024Publication date: May 16, 2024Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
-
Patent number: 11985825Abstract: A memory array device includes a stack of transistors over a semiconductor substrate, a first transistor of the stack being disposed over a second transistor of the stack. The first transistor includes a first memory film along a first word line and a first channel region along a source line and a bit line, the first memory film being disposed between the first channel region and the first word line. The second transistor includes a second memory film along a second word line and a second channel region along the source line and the bit line, the second memory film being disposed between the second channel region and the second word line. The memory array device includes a first via electrically connected to the first word line and a second via electrically connected to the second word line, the second staircase via and the first staircase via having different widths.Type: GrantFiled: April 15, 2021Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Han Lin, Feng-Cheng Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Yu-Ming Lin, Han-Jong Chia
-
Patent number: 11961769Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.Type: GrantFiled: November 7, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
-
Patent number: 11942145Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.Type: GrantFiled: May 6, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chuan Yang, Jui-Wen Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu, Lien Jung Hung, Ping-Wei Wang
-
Publication number: 20240097010Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Sai-Hooi Yeong, Sheng-Chen Wang, Bo-Yu Lai, Ziwei Fang, Feng-Cheng Yang, Yen-Ming Chen
-
Publication number: 20240098959Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.Type: ApplicationFiled: November 22, 2023Publication date: March 21, 2024Inventors: Kai-Hsuan Lee, Chia-Ta Yu, Cheng-Yu Yang, Sheng-Chen Wang, Sai-Hooi Yeong, Feng-Cheng Yang, Yen-Ming Chen
-
Patent number: 6987805Abstract: A method is provided for encoding K>1 sequentially presented video pictures. Each of the K pictures is divided into an m>1 row×n>1 column array of non-overlapping coding units of equal sizes. Each coding unit occupies a respective coding unit position in the picture from which it was divided. An arbitrary, pseudo random pattern of coding units is selected for refreshing during each of the K pictures. Each pattern selected during any given one of the K pictures includes a sequence of one or more coding units of the array. In addition, the pixels of each coding unit selected for refreshing during a kth picture occupy different pixel positions than each coding unit selected for refreshing during a preceding one of the 1st to (k?1)th pictures of the K pictures. Furthermore, each pixel position of a moving picture image formed from the K pictures is selected for refreshing once over the sequence of K pictures.Type: GrantFiled: September 24, 1999Date of Patent: January 17, 2006Assignee: LSI Logic CorporationInventors: Charles Weckel, Hervé Brelay, Feng-Ming Wang
-
Patent number: 5973758Abstract: An encoder system includes an internal counter (PTS or presentation time stamp counter). The counter provides information which enables the encoder system to resynchronize itself in the event synchronization with the video input stream is lost. Preferably, the counter is implemented in software. The encoder system also include a comparator (preferably implemented in software). The comparator is able to determine if particular regions of the input video stream have been captured at an expected time according to the internal counter within a predetermined error window by comparing the actual capture time with the expected capture time. In general, if the encoder system is synchronized with the incoming video stream, each successive blanking or active region will be captured at its expected time according to the internal counter within a predetermined error window. In this event, the timing of the various modules of the encoder system (e.g., preprocessing, spatial encoding, etc.Type: GrantFiled: January 14, 1998Date of Patent: October 26, 1999Assignee: C-Cube Microsystems, Inc.Inventors: Kourosh Soroushian, Feng-Ming Wang, Siok Huang Tay
-
Patent number: 5193004Abstract: In accordance with the invention, a method, for coding multi-mode predictive interpolative coded fields of video, includes the steps of:(a) providing a current field of interlaced pixel data, and past and future fields of such data;(b) providing estimated pixel data at omitted line positions in the past and future fields of data to form enhanced fields of pixel data;(c) comparing a block of pixel data from the current field with corresponding blocks of data from such past and future fields to derive motion vector signals indicative of best matched blocks of data;(d) developing pixel error signals representing pixel by pixel errors based on utilization of best matched blocks in different modes for comparison with the block of pixel data from the current field and developing best mode signals indicative of which of such modes represents the least overall error; and(e) providing the best mode signals, motion vector signals, pixel error signals, and the future odd field of data for transmission for use by a decodType: GrantFiled: December 3, 1990Date of Patent: March 9, 1993Assignee: The Trustees of Columbia University in the City of New YorkInventors: Feng Ming Wang, Dimitris Anastassiou
-
Patent number: 5134480Abstract: Deinterlacing systems and methods useful with television and other interlaced data signals derive values for pixels on missing lines using best matching values for blocks of pixels through time-recursive comparison of current pixels block values with such values for prior frames of data and also with later frames. Noise propagation is attenuated by mixing of current interpolated pixel data and memory size efficiency is achieved by comparisons based on blocks of pixels, with the block size adjustable for data accuracy. Use of chrominance signal comparisons and reduced data rate coding techniques provide added capabilities to the deinterlacing systems and methods.Type: GrantFiled: August 31, 1990Date of Patent: July 28, 1992Assignees: The Trustees of Columbia University in the City of New York, American Telephone and Telegraph CompanyInventors: Feng-Ming Wang, Dimitris Anastassiou, Arun N. Netravali