Abstract: A method of interleaving blocks of indexed data of varying length is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon a desired Interleaver length L; and adapting the selected basic Interleaver to produce an Interleaver having the desired Interleaver length L.

Abstract: An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a short LDPC code by shortening longer mother codes. The short LDPC code has an outer Bose Chaudhuri Hocquenghem (BCH) code. According to another aspect, for an LDPC code with code rate of 3/5 utilizing 8-PSK (Phase Shift Keying) modulation, an interleaver provides for interleaving bits of the output LDPC code by serially writing data associated with the LDPC code column-wise into a table and reading the data row-wise from right to left. The above approach has particular application in digital video broadcast services over satellite.

Abstract: A method and apparatus for encoding data for transmission in a communication system provides increased efficiency in bandwidth utilization through higher data rates, lower error rates, lower power levels, and/or increased capacity. A set of orthogonal codes is partitioned into subsets. The data to be transmitted is partitioned into packets of bit sequences, each of which is mapped to an orthogonal code in an assigned subset. The number of members in a particular subset is determined by the relative transmission requirements of the data signal the subset will be used to encode.

Abstract: A method and apparatus for providing an asymmetrical backwards compatible communications signal that is capable of being decoded by QPSK and OQPSK receivers as well as PSK and QAM receivers is provided. The invention comprises a timing error accumulator coupled to a first bit stream. The first bit stream includes content that is common to the QPSK/OQPSK receiver and to the PSK/QAM receiver. A phase error accumulator is coupled to a second bit stream and adjusts the phase of symbols in the second bit stream. A phase and timing error compensator is coupled to the phase error accumulator and the timing error accumulator and adjusts the first and second bit streams received from the phase error accumulator and the timing error accumulator in order to reduce timing and phase errors. A higher order modulator coupled to the phase- and timing error compensator is also provided. The higher order modulator processes the first and second bit streams to provide the asymmetrical backwards compatible signal.

Abstract: An approach is provided for efficiently decoding low density parity check (LDPC) codes. An LDPC decoder includes a memory for storing a mapped matrix that satisfies a plurality of parallel decodable conditions for permitting a lumped memory structure. Additionally, the decoder includes a parallel processors accessing edge values from the stored mapped matrix decode the LDPC codes. The above approach has particular applicability to satellite broadcast systems.

Abstract: An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity check matrix to be lower triangular and/or satisfying other requirements such that the communication between bit nodes and check nodes of the decoder is simplified. Further, a cyclic redundancy check (CRC) encoder is supplied to encode the input signal according to a CRC code. This approach has particular application in digital video broadcast services over satellite.

Abstract: An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For a rate 3/5 code, the approach provides a degree profile that yields reduced memory requirements for storage of the edge values without significantly affecting the performance with respect to an “unmodified” rate 3/5 code. The relevant parameters for the reduced memory LDPC codes are as follows: q=72, nldpc=64800, kldpc=nBCH=38880, kBCH=38688. The above approach has particular application in digital video broadcast services over satellite.

Abstract: A method and apparatus for providing an asymmetrical backwards compatible communications signal that is capable of being decoded by QPSK and OQPSK receivers as well as PSK and QAM receivers is provided. The invention comprises a timing error accumulator coupled to a first bit stream. The first bit stream includes content that is common to the QPSK/OQPSK receiver and to the PSK/QAM receiver. A phase error accumulator is coupled to a second bit stream and adjusts the phase of symbols in the second bit stream. A phase and timing error compensator is coupled to the phase error accumulator and the timing error accumulator and adjusts the first and second bit streams received from the phase error accumulator and the timing error accumulator in order to reduce timing and phase errors. A higher order modulator coupled to the phase and timing error compensator is also provided. The higher order modulator processes the first and second bit streams to provide the asymmetrical backwards compatible signal.

Abstract: An approach is provided for decoding a low density parity check (LDPC) coded signal. Edge values associated with a structured parity check matrix used to generate the LDPC coded signal are retrieved from memory. The edge values specify the relationship of bit nodes and check nodes, and are stored within memory according to a predetermined scheme that permits concurrent retrieval of a set of the edge values. A decoded signal corresponding to the LDPC coded signal is output based on the retrieved edge values.

Abstract: An approach is provided for encoding short frame length Low Density Parity Check (LDPC) codes. An encoder generates a LDPC code having an outer Bose Chaudhuri Hocquenghem (BCH) code. Structure is imposed on the LDPC codes by restricting portion part of the parity check matrix to be lower triangular and/or satisfying other requirements such that the communication between bit nodes and check nodes of the decoder is simplified. Further, a cyclic redundancy check (CRC) encoder is supplied to encode the input signal according to a CRC code. This approach has particular application in digital video broadcast services over satellite.

Abstract: An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For a rate 3/5 code, the approach provides a degree profile that yields reduced memory requirements for storage of the edge values without significantly affecting the performance with respect to an “unmodified” rate 3/5 code. The relevant parameters for the reduced memory LDPC codes are as follows: q=72, nldpc=64800, kldpc=nBCH=38880, kBCH=38688. The above approach has particular application in digital video broadcast services over satellite.

Abstract: An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check Matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The information is organized in tabular form, wherein each row represents occurrences of one Values within a first column of a group of columns of the parity check matrix. The rows correspond to groups of columns of the parity check matrix, wherein subsequent columns within each of the groups are derived according to a predetermined operation. An LDPC coded signal is output based on the stored information representing the parity check matrix.

Abstract: An approach is provided for decoding a low density parity check (LDPC) coded signal. Edge values associated with a structured parity check matrix used to generate the LDPC coded signal are retrieved from memory. The edge values specify the relationship of bit nodes and check nodes, and are stored within memory according to a predetermined scheme that permits concurrent retrieval of a set of the edge values. A decoded signal corresponding to the LDPC coded signal is output based on the retrieved edge values.

Abstract: An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The information is organized in tabular form, wherein each row represents occurrences of one values within a first column of a group of columns of the parity check matrix. The rows correspond to groups of columns of the parity check matrix, wherein subsequent columns within each of the groups are derived according to a predetermined operation. An LDPC coded signal is output based on the stored information representing the parity check matrix.

Abstract: Method and apparatus for implementing LDPC codes in an IEEE 802.11 standard system configured to operate in a Multiple-Input, Multiple-Output (MIMO) schema. A method in accordance with the present invention comprises defining a base LDPC code, having a length equal to an integer number of data carriers in an ODFM symbol, transmitting the base LDPC code over a plurality of sub-carriers, wherein the base code is transmitted at an expected phase on sub-carriers specified by the IEEE 802.11 standard system, and transmitting the base LDPC code on other sub-carriers than those specified by the IEEE 802.11 standard system, wherein the base LDPC code on the other sub-carriers is transmit offset in phase from the base LDPC code on the specified sub-carriers.

Abstract: An approach is provided for minimizing co-channel interference in a communication system is disclosed. A header of a first frame is scrambled based on a first unique word. A header of a second frame is scrambled based on a second unique word. The first frame including the corresponding scrambled header and the second frame including the corresponding scrambled header are transmitted, respectively, over adjacent co-channels of the communication system. Each of the frames further includes a payload and a pilot block. The payload and the pilot block of the first frame are scrambled based on a first scrambling sequence. The payload and the pilot block of the second frame are scrambled based on a second scrambling sequence. The above arrangement is particularly suited to a digital satellite broadcast and interactive system.

Abstract: An approach is provided for minimizing co-channel interference in a communication system is disclosed. A header of a first frame is scrambled based on a first unique word. A header of a second frame is scrambled based on a second unique word. The first frame including the corresponding scrambled header and the second frame including the corresponding scrambled header are transmitted, respectively, over adjacent co-channels of the communication system. Each of the frames further includes a payload and a pilot block. The payload and the pilot block of the first frame are scrambled based on a first scrambling sequence. The payload and the pilot block of the second frame are scrambled based on a second scrambling sequence. The above arrangement is particularly suited to a digital satellite broadcast and interactive system.

Abstract: An approach is provided for minimizing co-channel interference in a communication system is disclosed. A header of a first frame is scrambled based on a first unique word. A header of a second frame is scrambled based on a second unique word. The first frame including the corresponding scrambled header and the second frame including the corresponding scrambled header are transmitted, respectively, over adjacent co-channels of the communication system. Each of the frames further includes a payload and a pilot block. The payload and the pilot block of the first frame are scrambled based on a first scrambling sequence. The payload and the pilot block of the second frame are scrambled based on a second scrambling sequence. The above arrangement is particularly suited to a digital satellite broadcast and interactive system.

Abstract: An approach for performing synchronization is provided. Phase and timing offsets are first estimated in order to calculate a frequency offset. A receiver processes a signal received from a satellite and determine offset information. The receiver includes a phase estimator for estimating a phase offset of the received signal, a timing estimator for estimating a timing offset of the received signal, and a frequency estimator for deriving a frequency offset from the phase and timing offset. A determination is made as to whether the sampling was done at a peak wave point of the data.

Abstract: An approach is provided for transmitting messages using low density parity check (LDPC) codes. Input messages are encoded according to a structured parity check matrix that imposes restrictions on a sub-matrix of the parity check matrix to generate LDPC codes. The LDPC codes are transmitted over a radio communication system (e.g., satellite network), wherein a receiver communicating over the radio communication system is configured to iteratively decode the received LDPC codes according to a signal constellation associated with the LDPC codes. The receiver is configured to iteratively regenerating signal constellation bit metrics after one or more decoding iterations.