Patents by Inventor Feng Yin

Feng Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210376231
    Abstract: A magnetic tunnel junction (MTJ) memory cell and a metallic etch mask portion are formed over a substrate. At least one dielectric etch stop layer is deposited over the metallic etch mask portion, and a via-level dielectric layer is deposited over the at least one dielectric etch stop layer. A via cavity may be etched through the via-level dielectric layer, and a top surface of the at least one dielectric etch stop layer is physically exposed. The via cavity may be vertically extended by removing portions of the at least one dielectric etch stop layer and the metallic etch mask portion. A contact via structure is formed directly on a top surface of the top electrode in the via cavity to provide a low-resistance contact to the top electrode.
    Type: Application
    Filed: March 12, 2021
    Publication date: December 2, 2021
    Inventors: Yu-Feng YIN, Tai-Yen PENG, An-Shen CHANG, Han-Ting TSAI, Qiang FU, Chung-Te LIN
  • Publication number: 20210276954
    Abstract: The present invention relates to a process for preparing 3-pyrrolidine carboxylic acid derivatives, and particularly a simple process for preparing 5-substituted 3-pyrrolidine carboxylic acid derivatives. In addition, the present invention relates to a novel pyrrolidine carboxylic acid derivative, its manufacture, pharmaceutical compositions containing it and its use as a catalyst.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 9, 2021
    Applicant: OKINAWA INSTITUTE OF SCIENCE AND TECHNOLOGY SCHOOL CORPORATION
    Inventors: Fujie TANAKA, Feng YIN
  • Publication number: 20210268940
    Abstract: A vehicle seat and an angle adjustment device thereof. The angle adjustment device comprises an unlock cam (3), a ratchet wheel (2) provided with internal teeth, and a plurality of slide blocks (4) disposed circumferentially and provided with external teeth. The angle adjustment device further comprises a plurality of extension and retraction blocks (6) corresponding to the slide blocks (4), wherein the extension and retraction block (6) is capable of driving the slide block (4) to move outwards in a radial direction so as to engage the internal teeth with the external teeth. A second elastic member (52) is provided between two adjacent extension and retraction blocks (6), and two ends of the second elastic member (52) in a deformation direction are respectively connected to the unlock cam (3) and the extension and retraction block (6).
    Type: Application
    Filed: August 3, 2018
    Publication date: September 2, 2021
    Inventors: Shuangqiang LI, Zili LEI, Xianhu LUO, Feng YIN, Wei DENG
  • Publication number: 20210167179
    Abstract: A semiconductor structure includes a metal gate structure comprising a gate dielectric layer and a gate electrode, a conductive layer disposed over the metal gate structure, and a contact feature in direct contact with the top portion of the conductive layer, where the conductive layer includes a bottom portion disposed below a top surface of the metal gate structure and a top portion disposed over the top surface of the metal gate structure, and where the top portion laterally extends beyond a sidewall of the bottom portion.
    Type: Application
    Filed: February 15, 2021
    Publication date: June 3, 2021
    Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
  • Patent number: 10988446
    Abstract: The present invention relates to a process for preparing 3-pyrrolidine carboxylic acid derivatives, and particularly a simple process for preparing 5-substituted 3-pyrrolidine carboxylic acid derivatives. In addition, the present invention relates to a novel pyrrolidine carboxylic acid derivative, its manufacture, pharmaceutical compositions containing it and its use as a catalyst.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: April 27, 2021
    Assignee: OKINAWA INSTITUTE OF SCIENCE AND TECHNOLOGY SCHOOL CORPORATION
    Inventors: Fujie Tanaka, Feng Yin
  • Patent number: 10923573
    Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
  • Publication number: 20200394744
    Abstract: There is provided a method for predicting a port-stay duration of a vessel at a port. The method includes: determining a plurality of port-stay components of the port-stay duration; determining a regression sequence of the plurality of port-stay components, comprising modeling a first port-stay component and each of a plurality of second port-stay components, determining the regression sequence of the plurality of port-stay components based on a relative measure associated to each of the plurality of second port-stay components; modeling each of the plurality of port-stay components in sequence in accordance with the regression sequence determined to obtain a first plurality of sequentially modeled port-stay components; modeling a first port-stay duration based on the first plurality of sequentially modeled port-stay components to obtain a first port-stay duration model; and predicting the port-stay duration based on the first port-stay duration model.
    Type: Application
    Filed: March 28, 2019
    Publication date: December 17, 2020
    Inventors: Haiyan Xu, Xiuju Fu, Xiao Feng Yin, Siow Mong Rick Goh, Wanbing Zhang
  • Publication number: 20200388504
    Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, the gate electrode including at least a first metal; a conductive layer formed above the gate electrode, the conductive layer including an alloy layer, the alloy layer including at least the first metal and a second metal different from the first metal, the alloy layer extending from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure; and a contact feature disposed above the metal gate structure, wherein the contact feature is in direct contact with a top surface of the conductive layer.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Pang-Sheng Chang, Yu-Feng Yin, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao, Chia-Yang Hung, Chia-Sheng Chang, Shu-Huei Suen, Jyu-Horng Shieh, Sheng-Liang Pan, Jack Kuo-Ping Kuo, Shao-Jyun Wu
  • Patent number: 10755945
    Abstract: A method includes forming a metal gate structure, wherein the metal gate structure includes a gate dielectric layer and a gate electrode; performing a surface treatment to a top surface of the metal gate structure, wherein the surface treatment converts a top portion of the gate electrode to an oxidation layer; forming a conductive layer above the gate electrode, wherein the forming of the conductive layer includes substituting oxygen in the oxidation layer with a metallic element; and forming a contact feature above the metal gate structure, wherein the contact feature is in direct contact with the conductive layer.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pang-Sheng Chang, Yu-Feng Yin, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao, Chia-Yang Hung, Chia-Sheng Chang, Shu-Huei Suen, Jyu-Horng Shieh, Sheng-Liang Pan, Jack Kuo-Ping Kuo, Shao-Jyun Wu
  • Patent number: 10676468
    Abstract: Disclosed are novel N-(3-heteroarylaryl)-4-arylarylcarboxamides and analogs thereof, represented by the Formula I: wherein C cyclic group, D1-D4, Q1, Q2, R5 are defined herein. Compounds having Formula (I) are hedgehog pathway inhibitors. Therefore, compounds of the invention may be used to treat clinical conditions that are responsive to the inhibition of hedgehog activity, such as cancer.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: June 9, 2020
    Assignee: Impact Therapeutics, Inc.
    Inventors: Suixiong Cai, Ye Edward Tian, Sishun Kang, Zheng Meng, Chengyun Gu, Feng Yin, Shengzhi Chen, Yang Zhang, Xiuyan Zhang, Hongqiang Fei, Dongmei Wang
  • Publication number: 20200059369
    Abstract: An example for determining consensus by Parallel Proof of Voting (PPoV) in a consortium blockchain includes causing each bookkeeping node to generate and publish a block to a consortium blockchain network. After collecting all the block generated in the previous step, the consortium node votes send a total voting message (the hash value of each block, as well as the agreed opinion and signature) to the leader node. The leader node counts the voting results and random selects the next leader node, which publishes the block group header to the consortium blockchain network. When a blockchain node receives the block generated by the bookkeeping nodes and the block group header generated by the leader node, it will store them in the database as a block group.
    Type: Application
    Filed: August 13, 2019
    Publication date: February 20, 2020
    Inventors: Hui Li, Han Wang, Jiansen Huang, Huajun Ma, Feng Yin, Yongjie Bai, Kaixuan Xing, Kedan Li, Hanxu Hou
  • Patent number: 10560805
    Abstract: A method performed by a network node or a wireless communications device for determining a reporting threshold related to proximity based positioning in a wireless communications network. For each of a plurality of candidate reporting thresholds the network node or the wireless communications device calculates a corresponding localization accuracy metric based on a deployment information related to a deployment of the wireless communications network, an evaluation position related to the evaluation of a received signal, a propagation model relating the evaluation position and the evaluation of the received signal, and the respective candidate reporting threshold. The network node or the wireless communications device then determines the reporting threshold based on the plurality of corresponding localization accuracy metrics.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: February 11, 2020
    Assignee: Telefonaktiebolaget LM Ericcson (publ)
    Inventors: Fredrik Gunnarsson, Feng Yin, Yuxin Zhao
  • Publication number: 20200020541
    Abstract: A method includes forming a metal gate structure, wherein the metal gate structure includes a gate dielectric layer and a gate electrode; performing a surface treatment to a top surface of the metal gate structure, wherein the surface treatment converts a top portion of the gate electrode to an oxidation layer; forming a conductive layer above the gate electrode, wherein the forming of the conductive layer includes substituting oxygen in the oxidation layer with a metallic element; and forming a contact feature above the metal gate structure, wherein the contact feature is in direct contact with the conductive layer.
    Type: Application
    Filed: July 16, 2018
    Publication date: January 16, 2020
    Inventors: Pang-Sheng Chang, Yu-Feng Yin, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao, Chia-Yang Hung, Chia-Sheng Chang, Shu-Huei Suen, Jyu-Horng Shieh, Sheng-Liang Pan, Jack Kuo-Ping Kuo, Shao-Jyun Wu
  • Publication number: 20200013866
    Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
  • Patent number: 10418453
    Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: September 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
  • Publication number: 20190270732
    Abstract: Disclosed are 1-(arylmethyl)quinazoline-2,4(1H,3H)-diones represented by the Formula (I): wherein Ar, R1-R6 are defined herein. Compounds having Formula (I) are PARP inhibitors. Therefore, compounds of the invention may be used to treat clinical conditions that are responsive to the inhibition of PARP activity.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 5, 2019
    Applicant: IMPACT Therapeutics, Inc.
    Inventors: Sui Xiong CAI, Ye Edward TIAN, Haijun DONG, Qingbing XU, Lizhen WU, Lijun LIU, Yangzhen JIANG, Qingli BAO, Guoxiang WANG, Feng YIN, Chengyun GU, Xiuhua HU, Xiaozhu WANG, Sishun KANG, Shengzhi CHEN
  • Patent number: 10316027
    Abstract: Disclosed are 1-(arylmethyl)quinazoline-2,4(1H,3H)-diones represented by the Formula (I): wherein Ar, R1-R6, are defined herein. Compounds having Formula (I) are PARP inhibitors. Therefore, compounds of the invention may be used to treat clinical conditions that are responsive to the inhibition of PARP activity.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 11, 2019
    Assignee: Impact Therapeutics, Inc.
    Inventors: Sui Xiong Cai, Ye Edward Tian, Haijun Dong, Qingbing Xu, Lizhen Wu, Lijun Liu, Yangzhen Jiang, Qingli Bao, Guoxiang Wang, Feng Yin, Chengyun Gu, Xiuhua Hu, Xiaozhu Wang, Sishun Kang, Shengzhi Chen
  • Publication number: 20190169125
    Abstract: The present invention relates to a process for preparing 3-pyrrolidine carboxylic acid derivatives, and particularly a simple process for preparing 5-substituted 3-pyrrolidine carboxylic acid derivatives. In addition, the present invention relates to a novel pyrrolidine carboxylic acid derivative, its manufacture, pharmaceutical compositions containing it and its use as a catalyst.
    Type: Application
    Filed: September 28, 2016
    Publication date: June 6, 2019
    Applicant: OKINAWA INSTITUTE OF SCIENCE AND TECHNOLOGY SCHOOL CORPORATION
    Inventors: Fujie TANAKA, Feng YIN
  • Publication number: 20190157409
    Abstract: A conductive layer is formed between a metal gate structure, which includes a high-k gate dielectric layer and a gate electrode, and a contact feature. The conductive layer can be selectively deposited on a top surface of the gate electrode or, alternatively, non-selectively formed on the top surface of the gate electrode and the gate dielectric layer by controlling, for example, time of deposition. The conductive layer can have a bottom portion embedded into the gate electrode. The conductive layer and the contact feature can include the same composition, though they may be formed using different deposition techniques.
    Type: Application
    Filed: January 30, 2018
    Publication date: May 23, 2019
    Inventors: Chao-Hsun Wang, Yu-Feng Yin, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao
  • Patent number: 10114731
    Abstract: An improved method of analyzing software issues may include retrieving and storing selected data elements from the operating system kernel data prior to performing a memory dump. The method of retrieving the selected kernel data may include creating a thread dedicated to collecting the data and storing it in a memory location for analysis after the memory dump. The operating system kernel data may be analyzed in conjunction with the prior art dump data to identify a root cause of the software issue.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: October 30, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Xiaohua Fan, Feng Yin, Xiaogang Wang, Dazhi Dong, Binhua Lu